Compact Implementation of the RISC-V RV32EMC ISA

Overview

Cortus have applied their many years of processor design expertise to the RISC-V ISA. Concentrating on the needs of the embedded designer and leveraging the success of their APS family of processors.

The APS3V processor offers the RISC-V ISA RV32EMC features, with the full integer instruction set, compressed instructions and multiply and divide. In addition it implements the privilege features with Machine and User modes.

The Cortus APS1V processor is designed to be both power and silicon efficient. The standard implementation requires 12 634 gates.

The Cortus APS1V processor features a Harvard architecture with AXI4 Lite bus interfaces. This ensures wide compatibility with other peripheral IP, allowing the standard peripherals from Cortus to be complemented by other IP.

Full debug support is implemented through Cortus’ standard debug interface and tools (GDB and OpenOCD).

Key Features

RISC-V 32 bit ISA (RV32)
Embedded Instruction Set (E)
Compressed Instruction Set (C)
Integer Multiply & Divide (M)
Machine and User Modes
AXI4 Lite Bus (Instruction and Data)
Small Silicon Footprint
Full Peripheral Set
Hardware Breakpoints
Full Toolchain and IDE

Benefits

The Cortus APS1V processor is designed to be both power and silicon efficient. The standard implementation requires 12 000 gates.

Applications

Embedded Control
Encryption and Decryption
Wireless and Wireline Communication
Sensor Fusion
Machine Vision
Dual and Multi-core Systems

Deliverables

Full Verilog Source Code
Full Toolchain
Graphical Development Environment
Debugger
Standard Peripherals
Full Documentation
Complete Integration Guide
Supplied as Part of a Design Services Contract

Technical Specifications

Foundry, Node

All

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