Combined Power-On-Reset and Brown-Out-Reset in TSMC 40 ULP
Overview
Combined Power-On-Reset and Brown-Out-Reset in TSMC 40ULP process
Key Features
- Can be used to monitor 3.3V battery or voltage regulator output
- Monitored input voltage programmable from 0.55V to 3.3V
- Dual POR and BOR functions
- Low power mode for best consumption in sleep mode
Technical Specifications
Foundry, Node
TSMC 40nm uLP
Maturity
In Production
TSMC
In Production:
40nm
LP
Related IPs
- Combined Power-On-Reset and Brown-Out-Reset in TSMC 22ULL
- Combined Power-On-Reset and Brown-Out-Reset in SMIC 40EF
- Combined Power-On-Reset and Brown-Out-Reset in TSMC 22ULL
- PCIe 4.0 LP PHY in TSMC (N7) for Automotive
- 112G Ultra-Low Power VSR PHY in TSMC N5 for optical modules and accelerators
- Complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core