InCirT offers SerDes which can deliver up to 12.5Gbps per lane for bidirectional data transfer. It consists of programmable receiver front-end and transmitter.
The total architecture is highly integrable and can be adapted to the customer’s requirements easily. The small area (0.1 sq mm) and low power consumption per lane are the key features of it which can lead to increased data transfer by simply combining more physical lanes.
Bi-directional High speed interface lane up to 12.5Gbps
Overview
Key Features
- High data rate (Up to 12.5Gbps per lane)
- Programmable receiver frontend
- Programmable transmitter
- 5-bit controlled digital delay line in the receiver for high-speed clock
- Low power consumption per lane
- High degree of integrability
Applications
- High speed data converters such as DAC, ADC, etc.
- Network equipment
- Low-latency required applications
Deliverables
- Verilog simulation models: Functional abstract
- GDSII layout
- Integration support
- DRC, LVS reports
- Datasheet including characterization results
- LEF, CDL netlist for LVS
- Verification report
Technical Specifications
Foundry, Node
GlobalFoundries 22nm FDX
Maturity
GDSII
Availability
Now Available
GLOBALFOUNDRIES
Pre-Silicon:
22nm
FDX
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