IP Catalog > Peripheral IP > AMBA AHB / APB/ AXI IP > AMBA AHB / APB IP > AMBA APB Assertion IP

AMBA APB Assertion IP

Overview

AMBA APB Assertion IP provides an efficient and smart way to verify the AMBA APB designs quickly without a testbench. The SmartDV's AMBA APB Assertion IP is fully compliant with standard AMBA APB 3.0/4.0 Specification.

AMBA APB Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

AMBA APB Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Specification Compliance
    • Compliant to ARM AMBA APB 3.0/4.0 protocol
    • Supports all data and address widths.
    • Supports different transfer types including IDLE, WRITE and READ.
    • Supports unaligned and unmapped address accesses.
    • Support for APB4 protected accesses and write strobe signal.
  • Assertion IP features
    • Assertion IP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Master mode, Slave mode, Monitor mode and Constraint mode.
    • Supports Simulation mode (stimulus from SmartDV APB VIP) and Formal mode (stimulus from Formal tool).
    • Rich set of parameters to configure APB Assertion IP functionality.

    Benefits

    • Runs in every major formal and simulation environment.

    Block Diagram

    AMBA APB Assertion IP Block Diagram

    Deliverables

    • Detailed documentation of Assertion IP usage.
    • Documentation also contains User's Guide and Release notes.

    Technical Specifications

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