IP Catalog > Peripheral IP > AMBA AHB / APB/ AXI IP > AMBA AHB / APB IP > AMBA AXI4-Lite Assertion IP

AMBA AXI4-Lite Assertion IP

Overview

AMBA AXI4-Lite Assertion IP provides an smart way to verify the ARM AMBA AXI4-Lite component of a SOC or a ASIC. The SmartDV's AMBA AXI4-Lite Assertion IP is fully compliant with standard AMBA AXI4-Lite Specification and provides the following features.

AMBA AXI4-Lite Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

AMBA AXI4-Lite Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Specification Compliance
    • Compliant with the latest ARM AMBA AXI4-Lite Protocol Specification.
    • Supports all AXI4-Lite data and address widths.
    • Supports all protocol transfer types and response types.
    • Separate address, data and response phases. Separate read and write channels.
    • Write strobe support to enable sparse data transfer on the write data bus.
    • Unaligned address access support.
    • Ability to issue multiple outstanding transactions.
    • Out of order transaction completion support.
    • Protected accesses with normal/privileged, secure/non-secure and data/instruction.
    • Ability to configure the width of all signals.
    • Support for bus inactivity detection and timeout.
    • Configurable WID signal enable support.
    • Burst length of 1.
    • Write strobe support.
    • Data bus width of 32-bit or 64-bit.
    • Quality of Service signaling.
    • Multiple region interfaces.
    • User signaling support.
    • Supports unmapped region address accesses.
    • AWCACHE and ARCACHE Attributes.
  • Assertion IP features
    • Assertion IP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Master mode, Slave mode, Monitor mode and Constraint mode.
    • Supports Simulation mode (stimulus from SmartDV AXI4-Lite VIP) and Formal mode (stimulus from Formal tool).
    • Rich set of parameters to configure AXI4-Lite Assertion IP functionality.

    Benefits

    • Runs in every major formal and simulation environment.

    Block Diagram

    AMBA AXI4-Lite Assertion IP Block Diagram

    Deliverables

    • Detailed documentation of Assertion IP usage.
    • Documentation also contains User's Guide and Release notes.

    Technical Specifications

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