IP Catalog > Peripheral IP > AMBA AHB / APB/ AXI IP > AMBA AHB / APB IP > AMBA ACE4-Lite Assertion IP

AMBA ACE4-Lite Assertion IP

Overview

AMBA ACE4-Lite Assertion IP provides an smart way to verify the ARM AMBA ACE4-Lite component of a SOC or a ASIC. The SmartDV's AMBA ACE4-Lite Assertion IP is fully compliant with standard AMBA ACE4-Lite Specification and provides the following features.

AMBA ACE4-Lite Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

AMBA ACE4-Lite Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Specification Compliance
    • Compliant with the latest ARM AMBA ACE4-Lite Protocol Specification.
    • Supports all ACE4-Lite data and address widths.
    • Supports all protocol transfer types, burst types, burst lengths, burst sizes and response types.
    • Separate address, data and response phases. Separate read, write channels.
    • Support for burst-based transactions with only start address issued.
    • Write strobe support.
    • Narrow transfer support.
    • Unaligned address access support.
    • Ability to issue multiple outstanding transactions.
    • Out of order transaction completion support.
    • Protected accesses with normal/privileged, secure/non-secure and data/instruction.
    • Ability to configure the width of all signals.
    • Support for bus inactivity detection and timeout.
    • Configurable WID signal enable support.
    • Read data interleaving support with programmable interleave depth and programmable interleave size per transaction to allow fixed and variable data interleaving in a transaction.
    • Atomic access support with normal access and exclusive access.
    • Longer bursts up to 256 beats.
    • Quality of Service signaling.
    • Multiple region interfaces.
    • User signaling support.
    • Ability to break longer bursts into multiple shorter bursts.
    • Supports unmapped region address accesses.
    • AWCACHE and ARCACHE Attributes.
    • ACE4-Lite specific features
    • Supports functionality to verify ACE4-Lite.
    • Supports all ACE4-Lite transaction types.
    • Support for multiple outstanding ACE4-Lite transactions.
    • Supports all write/read responses.
    • Barrier transactions
    • Shareable and Non-shareable transactions.
    • Broadcast cache maintenance operations.
  • Assertion IP features
    • Assertion IP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Master mode, Slave mode, Monitor mode and Constraint mode.
    • Supports Simulation mode (stimulus from SmartDV ACE4-Lite VIP) and Formal mode (stimulus from Formal tool).
    • Rich set of parameters to configure ACE4-Lite Assertion IP functionality.

    Benefits

    • Runs in every major formal and simulation environment.

    Block Diagram

    AMBA ACE4-Lite Assertion IP Block Diagram

    Deliverables

    • Detailed documentation of Assertion IP usage.
    • Documentation also contains User's Guide and Release notes.

    Technical Specifications

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