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AES Key Expander

Overview

The KEXP IP core performs AES key expansion, and is an option for the AES, AES-P, AES-CCM and AES-GCM cores. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths. 

Two architectural versions are available to suit system requirements. The Standard version (KEXP-P) is more compact and is used with AES cores using a 32-bit datapath.  The Fast version (KEXP-F) achieves higher throughput in conjunction with AES cores using a 128-bit datapath.  

The KEXP core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs.  
 

Key Features

  • Satisfies Federal Information Processing Standard (FIPS) Publication 197 from the US National Institute of Standards and Technology (NIST)
  • Employs user-programmable key size of 128, 192 or 256 bits
  • Two architectural versions:
    • Standard is more compact: 32-bit data path size
    • Fast yields higher transmission rates: 128-bit data path
  • Suitable for use with AES cores
  • Simple, fully synchronous, reusable design
  • Available as fully functional and synthesizable VHDL or Verilog, or as a netlist for popular programmable devices
  • Complete deliverables include test benches, C model and test vector generator

Block Diagram

AES Key Expander Block Diagram

Technical Specifications

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