AES-CTR, 256-bit key, high-speed

Overview

XIP1103H from Xiphera is a high-speed Intellectual Property (IP) core implementing the Advanced Encryption Standard (AES) in Counter Mode (CTR).

The Counter mode of operation effectively turns a block cipher into a stream cipher, and provides a number of advantages from an implementation point of view. These include the ability to use the same key expansion functionality and datapath for both encryption and decryption, and the possibility to parallelize the FPGA-based implementation by unrolling and pipelining.

XIP1103H has been designed for easy integration with FPGA- and ASIC-based designs in a vendor-agnostic design methodology, and the functionality of XIP1103H does not rely on any FPGA manufacturer-specific features.

XIP1103H has also been successfully validated in the CAVP (Cryptographic Algorithm Validation Program) by NIST (National Institute for Standards and Technology).

Key Features

Moderate resource requirements: The entire XIP1103H requires less than 14000 Adaptive Lookup Modules (ALMs) (Intel® Cyclone®V), and does not require any multipliers or DSPBlocks. Contact sales@xiphera.com for ASIC resource requirements.
Performance: Despite its moderate size, XIP1103H achieves a throughput in the tens of Gbps range, for example 100+ Gbps in Xilinx® Virtex® UltraScale+™ FPGA family.
Standard Compliance: XIP1103H is fully compliant with both the Advanced Encryption Algorithm (AES) standard, as well as with the Counter Mode (CTR) standard.
128-bit and 256-bit Interfaces ease the integration of XIP1103H with other FPGA logic and/or control software.

Benefits

Fully digital design
Portable to any ASIC or FPGA technology
Fully standard compliant
Easy to integrate
Several bus interfaces available
IP core designed in-house at Xiphera
Technical support by the original designers and cryptographic experts
CAVP validated

Block Diagram

Applications

XIP1103H protects the confidentiality of the encrypted plaintext, and to additionally provide authenticity protection XIP1103H can be used as a building block in AES-GCM (Galois Counter Mode) (for example, Xiphera’s IP cores XIP1113B and XIP1113H have XIP1103H for confidentiality protection).
An alternative way to protect both confidentiality and authenticity is to use XIP1103H in combination with a keyed message authentication code (such as Xiphera’s KMAC IP core).

Deliverables

Please contact sales@xiphera.com for pricing and your preferred delivery method. XIP1103H can be shipped in a number of formats, including netlist, source code, or encrypted source code.
Additionally, synthesis scripts, a comprehensive testbench, and a detailed datasheet including an integration guide are included.

Technical Specifications

Foundry, Node

Any

Maturity

Hardware Tested

Availability

Immediate

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