Advanced Encryption Standard Module
Overview
The CC-AES-APB is a synthesisable Verilog model of a Advanced Encryption Standard module. The AES core can be efficiently implemented on FPGA and ASIC technologies.
Key Features
- AMBA APB3 bus
- Encryption and decryption
- ECB mode
- Programmable key length
- Fully synthesizable synchronous design with positive edge clocking
- DFT ready
Benefits
- Synthesizable RTL Verilog source code
- Technology independent IP Core
- Suitable for FPGA and ASIC
- Easy SoC integration
- Full implementation and maintenance support with individual approach
- Flexible licensing scheme
Block Diagram
Deliverables
- Verilog RTL source code
- Verification suite
- Datasheet and integration guide
- C-header file
- Constraints
- Technical support
Technical Specifications
Availability
Now
Related IPs
- Advanced Encryption Standard Module
- Ultra-Compact Advanced Encryption Standard (AES, FIPS-197) Core
- Advanced Encryption Standard En- / Decryption IP-Core
- Advanced Encryption Standard (AES-128) core with AMBA AHB interface
- Advanced Encryption Standard compliant with FIPS 197
- Ultra-Compact Data Encryption Standard (DES/3DES) Core