40LP High density dual port SRAM compiler with Vss booster feature
Overview
40LP High density dual port SRAM compiler with Vss booster feature
Technical Specifications
Short description
40LP High density dual port SRAM compiler with Vss booster feature
Vendor
Vendor Name
Foundry, Node
UMC 40nm
Maturity
Pre-Silicon release
UMC
Pre-Silicon:
40nm
,
40nm
LP
Related IPs
- Single Port SRAM compiler - Memory optimized for ultra low power and high density - Dual Voltage - compiler range up to 512 k
- Single Port SRAM compiler - Memory optimized for ultra low power and high density - Dual Voltage - compiler range up to 512 k
- Single Port SRAM compiler - Memory optimized for ultra high density and high speed - Dual Voltage - compiler range up to 640 k
- Single Port SRAM compiler - Memory optimized for ultra low power and high density - Dual Voltage - compiler range up to 512 k
- Single Port SRAM compiler - Memory optimized for ultra low leakage and high density - Dual Voltage - compiler range up to 640 k
- Dual Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 80 k