32-bit RISC-V embedded core with in-order single issue pipeline.
Optimized for low power and small area. Perfectly fits for embedded control.
32-bit RISC-V embedded core with in-order single issue pipeline
Overview
Key Features
- Configurable instruction set architecture:
- 32-bit RISC-V with 32 integer registers (I extension)
- Integer multiplication and division (M extension)
- Atomic operation support (A extension)
- Compressed mode for better code density (C extension)
- IEEE 754-2008 compliant single precision floating point (F extension)
- IEEE 754-2008 compliant double precision floating point (D extension)
- User mode interrupt handlers (N extension)
- Bit manipulation instructions support (B extension)
- Scalar cryptography instructions support (K extension)
- Digital signal processing instructions support (P extension)
- ECC memory protection (SEC-DED)
- Physical memory protection
- Integrated debug controller including HW breakpoints
- System bus access
- Compact JTAG support
- Trace support
- Power management support
- AXI/AHB configurable interfaces
- Performance
- 1.7 DMIPS/MHz
- 3.29 CoreMark/MHz
- Frequency
- 1.2 GHz (TSMC, 28nm HPC+, SSG corner)
Block Diagram
Technical Specifications
Related IPs
- 32-bit RISC-V core with in-order single issue pipeline for Linux-based systems
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- Very High Performance Embedded Microcontroller with Dual Issue Pipeline
- 64-bit RISC-V core with in-order dual issue pipeline based complex for Linux-based systems
- 8-stage, dual-issue, highly efficient in-order pipeline compatible with the RISC-V RV64GCV ISA
- 64-bit RISC-V core with in-order dual issue pipeline based complex for Linux-based systems