SCR3 is an efficient, silicon-proven, microcontroller-class, 32/64-bit RISC-V processor core. It is optimized for power-sensitive, small-area, embedded applications, that demand high performance.
SCR3 supports RISC-V standard "I" Integer, "M" Integer Multiplication and Division, "A" Atomic, "C" 16-bit Compressed, “B” Bit Manipulation, and “K” Scalar Cryptography extensions. SCR3 is equipped with an in-order 5-stage pipeline, a branch prediction unit for efficient code execution, PLIC, ACLINT, IPIC/CLIC units for efficient interrupt processing, and industry-standard AHB, AXI4, JTAG, and cJTAG interfaces for flexibility and compatibility.
The SCR3 memory subsystem includes a TCM unit, L1 and L2 caches, and an MPU unit with user and machine privilege modes that allow executing a variety of real-time operating systems. The processor core can operate in heterogenous clusters with up to 4 cores, offering hardware-level support for memory coherency and external accelerators integration.
SCR3 Key Features
| Core | |
|---|---|
| ISA | RV32/RV64(IMC[ABK]) Atomic Instructions [A], Bit Manipulation [B], Scalar Cryptography Instructions [K] — optional |
| Pipeline | 3-5 stages |
| Multicore Support (SMP) | Up to 4 cores with cache coherency |
| Branch Prediction Unit (BPU) | Static/Dynamic |
| Memory Subsystem | |
| Tightly-Coupled Memory (TCM) | Up to 256KB, error protection — ECC |
| L1 Cache | Up to 32KB + 32KB, error protection — parity/ECC |
| L2 Cache | From 128KB to 512KB, error protection — ECC |
| Memory Protection Unit (MPU) | Configurable, up to 32-region MPU |
| Interrupt Subsystem | |
| IPIC | Up to 32 interrupt lines |
| CLIC | Up to 4096 interrupt lines, up to 256 priority levels |
| PLIC | Up to 1023 interrupt lines, up to 256 priority levels |
| ACLINT | Up to 4096 interrupt lines |
| Debug Subsystem | |
| Interface | JTAG/cJTAG-compliant interface |
| Breakpoints | Up to 4 hardware breakpoints, unlimited software breakpoints support |
| Interfaces | |
| AXI | Master AXI4 AMBA standard interface |
| AHB | Master AHB AMBA standard interface |
| Timers and Counters | |
| Performance Monitoring | Up to 32 performance counters |
| Embedded 64-bit RTC Timer |
Machine- |
Development Tools
Syntacore Development Toolkit (SCR3 Optimized)
The SC-DT package is a ready-to-use software development kit containing pre-built and pre-configured tools that simplify software development for the SCR3 core. With SC-DT, you can take advantage of the pre-built tools and configurations to reduce the time and effort required to get up and running with SCR3. SC-DT supports Windows and Linux operating systems and includes:
- Eclipse IDE and Visual Studio Code plugin
- Compilers (GCC, clang/LLVM with microarchitecture optimizations)
- Debuggers (GDB, OCD)
- Simulator (QEMU)
- FreeRTOS
- HAL and BSP
- Application examples
- Benchmarks
- Documentation
Syntacore also supports and maintains the Zephyr operating system that is not part of the SC-DT package and is downloadable separately.
