25 Gb/s AES-ECB 128/192/256 Crypto Cores

Overview

Concurrent EDA AES cores implement the 128-bit block size NIST FIPS AES Algorithm. This full ECB implementation generates 128-bit blocks of data with support for 128/ 192/256-bit Cipher keys.

This core is fully pipelined and can process data at 25 Gb/s rates and interface directly with Xilinx FIFOs.

The Advanced Encryption Standard (AES) is the cryptographic algorithm that was selected by the National Institutes of Standards to become the standard means of encryption and is described in detail in NIST publication FIPS 197.

Key Features

Up to 25.6 Gb/s of continuous encryption/ decryption.
Executes at 200MHz with a 128-bit data path interface.
Available in Encrypt only, Decrypt only, or Encrypt/Decrypt.
Complete with extensive testbench and ModelSim execution script.
Optimized for Xilinx Virtex 4/5/6 FPGAs.

Benefits

Very high performance AES encryption/decription.
Optimized for Xilinx FPGAs.
Operates at 200MHz with 128-bit data path.
Native FIFO interfaces to ease integration.

Deliverables

The AES Encrypt Core is available in a range of configurations For verification, ModelSim test scripts and a VHDL test bench are provided.
All variations come as a VHDL or EDIF netlist.
Available under Xilinx SignOnce IP License.

Technical Specifications

Maturity

Mature

Availability

Now

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