Helion offer a suite of AES-GCM solutions which allow the user to choose a level of hardware acceleration which closely fits the requirements, therefore minimising the amount of logic resources required. Solutions are available covering all throughput requirements from less than 1Gbps right up to in excess of 30Gbps in any of the target technologies we support. Also available are combined solutions which implement AES-GCM together with other modes of AES such as AES-XTS (previously known as AES-XEX) or AES-CBC, where multi protocol support is desired.
These high performance cores are available in versions for use in ASIC, Altera and Xilinx FPGA, and in common with all Helion IP cores they have been designed with each technology firmly in mind to yield the very best and most efficient results.
To find out how these AES-GCM solutions can be used in your particular application, please contact Helion so that we can discuss the options in more detail.
AES-GCM cores
Overview
Key Features
- Implements Galois/Counter (GCM) authenticated encryption mode to NIST SP800-38D
- Supports all AES key sizes (128, 192, and 256 bits) with integrated key expansion
- 96-bit Nonce/IV support
- Performs AES and GHASH functions needed for GCM including final block padding, tag appending and checking
- Simple 8-bit data interface for easy system integration
- Suitable for use in IPsec, MACsec, IEEE1619.1 and other applications
- Available in multiple versions providing optimal area/performance AES-GCM solution in ASIC
Benefits
AES-GCM is an authenticated encryption block cipher mode which provides data confidentiality, integrity and origin authentication based on a single secret key, and is described formally in NIST Special Publication SP800-38D. The implementation of GCM described in this brief targets medium throughput applications, with emphasis on low resource usage and ease of use via a byte-wide interface.
The AES-GCM core integrates all of the underlying functions required to implement AES in GCM mode including round-key expansion, counter mode logic, hash length counters, final block padding, and tag appending and checking features. The only external logic required is to form the Nonce block from various application specific packet header fields. Support is provided for both optional header and zero-length payload, and configurable tag length, making the core suitable for IPsec (RFC4106), MACsec (IEEE802.1ae) and Tape Storage (IEEE1619.1) applications.
Block Diagram
Deliverables
- Fully synthesisable RTL source code
- VHDL/Verilog testbench with test vectors
- User documentation