2.5V 100MHz Oscillator Inline I/O Pad Set
Overview
The OSx_BI_032_12V oscillator is designed to generate an asynchronous on-chip clock signal with an appropriate external oscillator crystal. The design has been optimized for low power (1.5 uW typical), stability and minimum jitter using a general purpose 32KHz crystal. The design has been characterized to allow a variation of 4pF to 18pF on each pin.
Key Features
- Key features:
- ? Very low power (2.6 uW max)
- ? Bypass mode
- ? Power down (disable) mode
- ? Speed-up circuitry for fast startup
Deliverables
- a. Physical abstract in LEF format (.lef)
- b. Timing models in Synopsys Liberty formats (.lib and .db)
- c. Calibre compatible LVS netlist in CDL format (.cdl)
- d. GDSII stream (.gds)
- e. Behavioral Verilog (.v)
- f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- g. Databook (.pdf)
- h. Library User Guide - ESD Guidelines (.pdf)
Technical Specifications
Foundry, Node
GLOBALFOUNDRIES, 40nm
Maturity
Silicon Proven
Availability
Available Now
GLOBALFOUNDRIES
Silicon Proven:
40nm
LP
Related IPs
- 3.3V 100MHz Oscillator IO Inline Pad Set
- 2.5V 100MHz Oscillator Staggered I/O Pad Set
- 3.3V 100MHz Oscillator IO Inline Pad Set
- 2.5V 5V Tolerant GPIO Inline IO Pad Set
- 2.5V General Purpose Inline IO Pad Set
- CSMC13V33 process DUPIO, This library includes analog I/O cells and digital I/O cells and supports Inline DUP I/O pad.