1.6 Gbps DDR Programmable LVDS Transmitter/Receiver

Overview

090TSMC_LVDS_02 consists of transmitter (LVDSOUT), receiver (LVDSIN) and a bias. The LVDS transmitter consists of a current source (nominal 3.5mA) that drives the differential pair lines and common-mode regulator, which provides the output common-mode voltage signal equal 1.25V. The output current adjustment is defined by the digital code register ILVO<2:0>. The receiver has high DC input impedance, so the majority of driver current flows across the 100Ohm external termination resistor generating about 350mV across the receiver inputs. When the driver switches, it changes the direction of current flow across the resistor, thereby creating a valid logic state of “1” or “0”. That is, it transforms 35mV input signal to CMOS 1.8V output signal. The internal current setting is defined by digital code register ILVI<2:0>.

Key Features

TSMC 90 nm CMOS
1 V CMOS input logic signal
Output current digital 3-bit adjustment (from 0.75 mA to 6.5 mA)
1.6 Gbps (DDR MODE) switching rates for transmitter
Low power dissipation (1.4 mW) for receiver
Low power dissipation (16.56 mW) for transmitter
Conforms to TIA/EIA-644 LVDS standards
Military temperature range: from -60 °C to + 125 °C
Propagation delay 590 ps for transmitter
Propagation delay 500 ps for receiver
Internal current digital 3 bit adjustment (high inner current for high frequency, from 40 to 300 uA) for receiver
Portable to other technologies (upon request)

Applications

Point-to-point data transmission
Multidrop buses
Clock distribution
Backplane receiver
Backplane data transmission
Cable data transmission

Deliverables

Schematic or NetList
Abstract model (.lef and .lib files)
Layout view (optional)
Behavioral model (Verilog)
Extracted view (optional)
GDSII
DRC, LVS, antenna report
Test bench with saved configurations (optional)
Documentation

Technical Specifications

Foundry, Node

TSMC 90 nm CMOS Logic Process

Maturity

Silicon proven

Availability

Now

TSMC

Silicon Proven: 90nm zzz

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