Modulation/Demodulation IP

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Modulation/Demodulation IP cores enable easy transmission of digital data over an analog transport.

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Compare 152 Modulation/Demodulation IP from 36 vendors (1 - 10)
  • APB Pulse Width Modulator
    • The APB PWM Module is a standard APB peripheral that generates a programmable duty cycle output signal.
    • The frequency of the output waveform is either PCLK/256 or PCLK/4096, depending on whether a 4-bit prescaler is enabled.
    Block Diagram -- APB Pulse Width Modulator
  • Pulse Width Modulator
    • The PWM IP core implements a compact and highly flexible Pulse Width Modulator. The core generates a repeated pattern of pulse trains of run-time configurable period and duty cycle.
    • Those pulse trains can be used in a wide variety of applications including but not limited to motor control and LED dimming. They can also be filtered with a lowpass filter to implement Digital to Analog Converters (DAC).
    Block Diagram -- Pulse Width Modulator
  • VHF/ UHF/L (DVB-H, DMB and ISDB-T) RF Front-end
    • TSMC BiCMOS SiGe 180 nm technology
    • Direct conversion receiver
    • A few number of external components
    • 0.18 um SiGe BiCMOS technology
    Block Diagram -- VHF/ UHF/L (DVB-H, DMB and ISDB-T) RF Front-end
  • DVB-S2X Modulator
    • Compliant with DVB-S2 and DVB-S2X
    • Supports ACM, CCM, and VCM modes
    • Support for short and normal frames (16,200 bits and 64,800 bits)
    • Support for QPSK to 256-APSK
    • Support for very low SNR modes (VLSNR) optional
    Block Diagram -- DVB-S2X Modulator
  • DVB-RCS2 Multi-Carrier Receiver
    • Compliant with ETSI EN 301 545-2 (DVB-RCS2)
    • Support for Linear Modulation Bursts of Table A-1
    • Optional support for Spread-spectrum Linear Modulation Burst waveforms of Table A-2
    • Support for BPSK, QPSK, 8-PSK, 16-QAM
    Block Diagram -- DVB-RCS2 Multi-Carrier Receiver
  • DVB-S2X Demodulator
    • Compliant with DVB-S2 and DVB-S2X
    • Supports ACM, CCM, and VCM modes
    • Support for short and long blocks (16,200 bits and 64,800 bits)
    • Support for QPSK to 256-APSK
    Block Diagram -- DVB-S2X Demodulator
  • CCSDS SCCC Turbo Encoder and Decoder
    • Burst-to-burst on-the-fly configuration
    • High payload block length granularity (between 5,758 and 43,678 bits)
    • High code rate granularity (code rates between 0.36 and 0.90)
    • Configurable amount of turbo decoding iterations for trading off throughput and error correction performance
    Block Diagram -- CCSDS SCCC Turbo Encoder and Decoder
  • CCSDS 131.2 Wideband Modulator
    • Compliant with CCSDS 131.2-B-1
    • Supports ACM mode
    • Supports roll-off factors 5%, 10%, 15%, 20%, 25% to 35%
    Block Diagram -- CCSDS 131.2 Wideband Modulator
  • CCSDS 131.2 Wideband Demodulator
    • Compliant with CCSDS 131.2-B-1
    • Supports ACM mode
    • Supports roll-off factors 5%, 10%, 15%, 20%, 25% and 35%
    • Support for blocks with pilots only
    Block Diagram -- CCSDS 131.2 Wideband Demodulator
  • LMS Adaptive Channel Equalizer
    • 17-tap T-spaced complex-arithmetic LMS signed-error Channel Equalizer
    • Adaptation bandwidth control (mu, step size)
    Block Diagram -- LMS Adaptive Channel Equalizer
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