Reconfigurable redefined with embedded FPGA core IP

By SemiWiki

February 15, 2016

On November 1, 1985, before anyone had heard the phrase field programmable gate array, Xilinx introduced what they called a “new class of ASIC” – the XC2064, with a whopping 1200 gates. Reconfigurable computing was born and thrived around the RAM-based FPGA, whose logic and input/output pins could be architected into a variety of applications and modified very quickly.

Soon, many of these applications leveraged the DSP capability of FPGAs. Some experimented with various topologies such as systolic arrays, and several interconnect strategies emerged including fixed crossbars and high pin count programmable interconnect chips. To tackle bigger data flow problems, FPGAs got bigger and faster, with more I/O pins and more look-up tables (LUTs) and advanced clocking and other architectural improvements.

While FPGAs grew, board and system computing shrank. Functions that used to require several boards shrank to a single-board computer, then shrank again to system-on-chip. FPGAs responded with their own SoC strategy, large enough to hold one or more processor cores interconnected with programmable logic. Reconfigurable computing is now often self-contained in a single high performance chip – in some cases, a very expensive one.

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