Memory Controller IP, battle field where Cadence and Synopsys are really fighting face to face. Today let's have a look at Cadence’s strategy
I have shared with you last year some strategic information released by Cadence in April about their IP strategy, more specifically about the launch of the DDR4 Controller IP. And try to understand Cadence strategy about Interface IP in general (USB, PCIe, SATA, DDRn, HDMI, MIPI…) and how Cadence is positioned in respect with their closest and more successful competitor in this field, Synopsys.
To read the full article, click here
Related Semiconductor IP
- UCIe RX Interface
- Very Low Latency BCH Codec
- 5G-NTN Modem IP for Satellite User Terminals
- 400G UDP/IP Hardware Protocol Stack
- AXI-S Protocol Layer for UCIe
Related Blogs
- Buying DDRn Controller IP AND Memory Model to the same IP vendor gives real TTM advantage
- Rambus HBM3 Controller IP Gives AI Training a New Boost
- Unlocking the Power of NAND ONFI Controller IP
- The Importance of Memory Architecture for AI SoCs
Latest Blogs
- Imagination Demonstrates DirectX Gaming on D-Series GPUs
- Embedded Security explained: Post-Quantum Cryptography (PQC) for embedded Systems
- Accreditation Without Compromise: Making eFPGA Assurable for Decades
- Synopsys Delivers First Complete UFS 5.0 and M‑PHY v6.0 IP Solution for Next‑Gen Storage
- World First: Synopsys MACsec IP Receives ISO/PAS 8800 Certification for Automotive and Physical AI Security