Memory Controller IP, battle field where Cadence and Synopsys are really fighting face to face. Today let's have a look at Cadence’s strategy
January 13, 2012
I have shared with you last year some strategic information released by Cadence in April about their IP strategy, more specifically about the launch of the DDR4 Controller IP. And try to understand Cadence strategy about Interface IP in general (USB, PCIe, SATA, DDRn, HDMI, MIPI…) and how Cadence is positioned in respect with their closest and more successful competitor in this field, Synopsys.
To read the full article, click here
Related Semiconductor IP
- 6-bit, 12 GSPS Flash ADC - GlobalFoundries 22nm
- LunaNet AFS LDPC Encoder and Decoder IP Core
- ReRAM NVM in DB HiTek 130nm BCD
- UFS 5.0 Host Controller IP
- PDM Receiver/PDM-to-PCM Converter
Related Blogs
- Buying DDRn Controller IP AND Memory Model to the same IP vendor gives real TTM advantage
- Rambus HBM3 Controller IP Gives AI Training a New Boost
- Unlocking the Power of NAND ONFI Controller IP
- The Importance of Memory Architecture for AI SoCs