Memory Controller IP, battle field where Cadence and Synopsys are really fighting face to face. Today let's have a look at Cadence’s strategy
January 13, 2012
I have shared with you last year some strategic information released by Cadence in April about their IP strategy, more specifically about the launch of the DDR4 Controller IP. And try to understand Cadence strategy about Interface IP in general (USB, PCIe, SATA, DDRn, HDMI, MIPI…) and how Cadence is positioned in respect with their closest and more successful competitor in this field, Synopsys.
To read the full article, click here
Related Semiconductor IP
- Special Purpose Low (Statistical) offset Operation Amplifier
- Rail to Rail Input and Output Operational Amplifier
- Special Purpose Low offset Operational Amplifier
- Special Purpose Low offset Operational Amplifier
- High Current, Low offset fast Operation Amplifier
Related Blogs
- Buying DDRn Controller IP AND Memory Model to the same IP vendor gives real TTM advantage
- Why do I need an AMBA 5 CHI Memory Controller?
- PCIe 5.0 Controller IP on FPGAs: Current and Future Use Cases
- Rambus Achieves PCI Express® (PCIe®) 5.0 Compliance for PCIe 5.0 Controller IP and Inspector PCIe 5.0 Interposer with Diagnostic IP
Latest Blogs
- Rivos and Canonical partner to deliver scalable RISC-V solutions in Data Centers and enable an enterprise-grade Ubuntu experience across Rivos platforms
- ReRAM-Powered Edge AI: A Game-Changer for Energy Efficiency, Cost, and Security
- Ceva-XC21 and Ceva-XC23 DSPs: Advancing Wireless and Edge AI Processing
- Cadence Silicon Success of UCIe IP on Samsung Foundry’s 5nm Automotive Process
- Empowering your Embedded AI with 22FDX+