MIPS针对高性能 RISC-V 应用级处理器选用 Imperas方案实现高级验证

Building on 35 years of innovation in RISC processor development, MIPS’ strategic move to RISC-V is supported by Imperas RISC-V Reference Models, Verification IP, and test suites

Oxford, United Kingdom, December 7^th, 2022 — Imperas Software Ltd., the leader in RISC-V simulation solutions, announced today that MIPS, a leading developer of highly scalable RISC processor IP, has selected Imperas to provide advanced RISC-V processor verification tools. Imperas supports advanced RISC-V processor verification solutions and methodology to seamlessly transition between issue detection and debug resolution within a unified testbench environment compatible with the leading SystemVerilog EDA tools.

Imperas solutions offer processor developers a unique and flexible framework for RISC-V processor verification. Imperas tools feature native support for the open standard RVVI (RISC-V Verification Interface), so developers can connect a new processor implementation to a testbench and leverage the growing ecosystem of verification IP. Imperas has also released a set of SystemVerilog functional coverage libraries that help developers achieve the coverage goals of an extensive RISC-V processor verification plan.

MIPS’ latest RISC-V based processor cores demand robust verification that covers extensive hardware features. MIPS’ latest RISC-V innovation, the eVocore P8700 multiprocessor, offers superscalar performance with multi-issue Out-of-Order (OoO) execution and multi-threading, and can scale to 64 clusters, 512 cores and 1,024 harts/threads. In addition, MIPS’ RISC-V eVocore I8500 is an enhanced in-order multiprocessing system combining multi-threading and a highly efficient triple issue pipeline, and is able to scale to 64 clusters, 512 cores and 2,048 harts/threads.

“At MIPS we are experienced in bringing advanced computing technology, such as hardware multi-threading, to market as applications-class processors,” said Don Smith, Vice President Engineering at MIPS. “As part of the strategic move to RISC-V, we fully appreciate the needs, implications and requirements for a high-quality verification solution. The Imperas Reference Model enables lock-step-compare with asynchronous events which is the foundation of our SystemVerilog testbench and verification methodology.”

“Since 2010, MIPS core IP deliverables have included the Imperas based ISS, and as a consequence our technology has helped to support many projects in applications such as high-performance wireless communications, networking, automotive and AI applications,” said Simon Davidmann, CEO at Imperas Software Ltd. “With MIPS’ strategic shift to RISC-V, we are pleased to continue our long-standing relationship with new technology and innovation for verification for the latest MIPS RISC-V based Applications-Class processors.”

Availability

The Imperas RISC-V processor verification technology is already in active use with many leading customers, some of which have working silicon and are now working on 2^nd generation designs. These customers, partners and users span the breadth of RISC-V adopters from open source to commercial; research to industrial; microcontrollers to high performance computing. A select sample of these includes - Codasip, EM Microelectronics (Swatch), NSITEXE (Denso), Nvidia Networking (Mellanox), OpenHW Group, MIPS, Seagate Technology, Silicon Labs, and Valtrix Systems, plus many others yet to be made public. Imperas RISC-V Verification solutions are available now, more details are available at Imperas.com/ImperasDV.

About RVVI

The open standard RVVI (RISC-V Verification Interface) offers adaptability and verification IP reuse for the expanding community of developers undertaking processor verification, the open specification is available on GitHub at https://github.com/riscv-verification/RVVI

RISC-V Summit 2022

Imperas is proud to be a contributing Diamond sponsor for the fifth annual RISC-V Summit, December 12-15, 2022, in San Jose, California. Imperas will showcase solutions for RISC-V processor verification, custom instruction design flows, and software development, including a keynote on RISC-V Processor verification plus many other activities.

For more information, please visit RISC-V Summit 2022.

Imperas RISC-V Summit Kickoff Party

Join Imperas at the RISC-V Summit Kickoff Party on December 12^th, open to all RISC-V Members and Summit Attendees. Connect with influencers, developers, and users in the RISC-V ecosystem as we celebrate the evolution of RISC-V and our community. The fun starts at 5:30pm on the Market Terrace, San Jose Convention Center. For more details visit Imperas RISC-V Summit Kickoff Party.

About MIPS

MIPS is a leading developer of highly scalable RISC processor IP for high-end automotive, computing and communications applications. With its deep engineering expertise built over 35 years and billions of MIPS-based chips shipped to-date, today the company is accelerating RISC-V innovation for a new era of heterogeneous processing. The company’s proven solutions are uniquely configurable, enabling semiconductor companies to hit exacting performance and power requirements and differentiate their devices. Visit www.mips.com.

About Imperas

Imperas is the leading provider of RISC-V processor models, hardware design verification solutions, and virtual prototypes for software simulation. Imperas, along with Open Virtual Platforms (OVP), promotes open-source model availability for a spectrum of processors, IP vendors, CPU architectures, system IP and reference platform models of processors and systems ranging from simple single core bare metal platforms to full heterogeneous multi-core systems booting SMP Linux. All models are available from Imperas at www.imperas.com/ and the Open Virtual Platforms (OVP) website.

For more information about Imperas, please see www.imperas.com.