晶心科技与 LDRA 携手合作,为晶心 RISC-V CPU安全关键软件提供集成工具套件
The integration helps developers to develop and manage applications in increasingly complex and safety-critical industries such as aerospace, automotive, railway, industrial, and medical on Andes RISC-V CPU solutions.
BANGALORE – January 19, 2023 — Andes Technology (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and founding premier member of RISC-V International, today announced the integration of AndeSight™ IDE with LDRA tool suite. The integration with LDRA’s comprehensive set of software standards compliance, testing, and verification tools helps developers to develop and manage applications in increasingly complex and safety-critical industries such as aerospace, automotive, railway, industrial, and medical on Andes RISC-V CPU solutions. This compliance results in safer, more secure, more efficient, and more capable software.
As part of the integration, the LDRA tool suite, along with the eclipse plugin, hooks into the AndeSight™ integrated development environment (IDE) to allow compilation, linking, programming, and execution in the AndeSight™ environments. The LDRA tool suite offers the built-in import capability to reduce the static analysis efforts of AndeSight™ project files via included paths, macros, and other settings. In addition, the LDRA tool suite performs dynamic analysis on simulator targets within the AndeSight™ IDE or on the AndeShape™ evaluation boards. This allows users to perform system and unit tests using the already available Andes infrastructure to provide a head start to developers.
The integration with the LDRA tool suite provides the following additional features to the AndeSight™ IDE:
- Source code static analysis
- Software dynamic analysis, including modified condition/decision coverage (MC/DC) on the host and target
- Software unit/integration testing on the host and target
- Improved code quality, safety, and security
- Reduced testing time and cost
LDRA Tool Suite Meets TÜV Certification
Functional safety standards consider the increasing use of tools for software application development and explicitly require such tools to be qualified. TÜV SÜD examined the quality and compliance of the software development processes and functional safety management of the LDRA tools to the given standards. TÜV assessed the suitability of the LDRA tools and associated user documentation as capable of supporting developers in safety-critical industries to achieve certification.
AndesCore™ N25F-SE Processor, the World First RISC-V CPU IP with ISO 26262 Full Compliance
The AndesCore™ N25F-SE is a safety-enhanced 32-bit RISC-V CPU core and is certified to be fully compliant with ISO 26262 ASIL B (Automotive Safety Integrity Level B) functional safety standards, including Parts 2, 4, 5, 8, and 9, for the development of automotive applications. The N25F-SE inherits the compact and performant design of the popular N25F. It supports standard IMACFD extensions including efficient integer and floating-point instructions and incorporates the Andes V5 extension instructions to further boost performance and reduce code size. To fully utilize the capabilities of the AndesCore™, the AndeSight™ IDE provides a comprehensive software solution that helps optimize code speed and code size and simplifies the development process by providing application development, debugging, analysis, compute libraries, OS awareness, and multicore development to developers.
“AndesCore™ N25F-SE ASIL B certified processor brings unique and competitive value to our RISC-V customers,” said Warren Chen, Senior Technical Marketing Manager, Andes Technology. “The exciting partnership with LDRA enables us to bring versatile solutions to the developers for safety-critical applications. We welcome the benefits the LDRA tool suite brings to the RISC-V community in accelerating the functional safety applications development.”
“Designers are currently moving toward real implementations of their RISC-V-based designs within multiple safety-critical industries,” said Ian Hennell, Operations Director, LDRA. “As the focus shifts to a software-driven architecture supported by top-notch analysis tools, the RISC-V software efforts require more than just enabling the existing architecture. With our integration with Andes Technology, developers can meet these requirements while making sure their software is safe and security-driven.”
About LDRA
For more than 45 years, LDRA has developed and driven the market for software that automates code analysis and software testing for safety-, mission-, security-, and business-critical markets. Working with clients to achieve early error identification and elimination, and full compliance with industry standards, LDRA traces requirements through static and dynamic analysis to unit testing and verification for a wide variety of hardware and software platforms. Boasting a worldwide presence, LDRA has headquarters in the United Kingdom, United States, Germany, and India coupled with an extensive distributor network. For more information on the LDRA tool suite, please visit www.ldra.com
About Andes Technology
Eighteen years in business and a Founding Premier member of RISC-V International, Andes is publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 3 billion in 2021 and continues to rise. By the end of 2021, the cumulative volume of Andes-Embedded™ SoCs has surpassed 10 billion. For more information, please visit https://www.andestech.com.
Related Semiconductor IP
- RISC-V Vector Extension
- RISC-V Real-time Processor
- RISC-V High Performance Processor
- 32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
- 32 Bit - Embedded RISC-V Processor Core
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