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Compare 85 IP from 31 vendors (1 - 10)
  • Single Port High-Speed Multi Bank SRAM Memory Compiler on GF 22FDX+
    • Ultra-Low Leakage - GLOBALFOUNDRIES low-leakage 6T L110 bit cells with High Vt and low leakage periphery to ensure minimal leakage and high yield.  
    • Multi-Bank Architecture - Memory split into 1 to 4 banks for reduced bit line length and enhanced timing. 
    • Ultra Low Power Standby - Built-in source biasing trims standby current to a minimum for data retention. 
    Block Diagram -- Single Port High-Speed Multi Bank SRAM Memory Compiler on GF 22FDX+
  • Single Port Low Leakage SRAM Memory Compiler on GF 22FDX+
    • Ultra-Low Leakage: High VT (HVT) and low leakage (LLHVT) devices are used with source biasing to minimize standby currents while operating at low voltage 
    • Bit Cell: Utilizes GlobalFoundries®  Ultra-Low Leakage, 6T(L110) bit cells to ensure high manufacturing yields  
    • Five Power Modes: High Performance, Low Leakage, Standby, Retention, and Power Off modes provide flexibility for power optimization 
    Block Diagram -- Single Port Low Leakage SRAM Memory Compiler on GF 22FDX+
  • Single Port Low Leakage SRAM Memory Compiler on GF 22FDX+
    • Ultra-Low Leakage: High VT (HVT) and low leakage (LLHVT) devices are used with source biasing to minimize standby currents while operating at low voltage 
    • Bit Cell: Utilizes GlobalFoundries®  Ultra-Low Leakage  6T (P110UL) bit cells to ensure high manufacturing yields 
    • Five Power Modes: High Performance, Low Leakage, Standby, Retention, and Power Off modes provide flexibility for power optimization 
    • Speed Grades: Three options to adjust the speed/leakage balance and optimize for high speed or low power operation 
    Block Diagram -- Single Port Low Leakage SRAM Memory Compiler on GF 22FDX+
  • Ultra-low power consumption out-of-order commercial-grade 64-bit RISC-V CPU IP
    • Dubhe-70 is a 9+ stage, 3-issue, out-of-order CPU IP that supports the rich RISC-V instruction set, RV64GCBH_Zicond_Zicbom_Zicboz_Zicbop.
    • With a score of 7.2 SPECInt2006/GHz, Dubhe-70 targets applications that require highly energy-efficient computation, including mobile, desktop, AI, and automotive.
    Block Diagram -- Ultra-low power consumption out-of-order commercial-grade 64-bit RISC-V CPU IP
  • Ultra-low power high dynamic range image sensor
    • Resolution: VGA (640 x 480)
    • Backside illuminated sensor
    • Pixel size: 6.3 μm x 6.3 μm
    • Fill factor: 83 %
    • Dynamic range: 120 dB intra-scene
    Block Diagram -- Ultra-low power high dynamic range image sensor
  • In Memory Computing (IMC)
    • CompuRAM™ provides In Memory Computing (IMC) that will enable solutions for computing at the Edge to be more power efficient. At present, sensor data often has to be sent from an IoT device to a server for processing, which creates a connectivity requirement and an unavoidable latency.
    • For time critical applications this is not acceptable and so there is a drive to do more computation within the device itself, i.e., AI processing at the Edge.
  • Ultra-low voltage, SRAM
    • SureCore has exploited its low power design capability to create a new range of ultra-low voltage, SRAM solutions, called PowerMiser™ Plus. 
    • Based on the market-leading, low dynamic power PowerMiser architecture, this dual rail product family can interface down to 0.45V, enabling customers to create innovative, low power products.
  • OCTARAM Memory Model
    • Supports OCTARAM memory devices from all leading vendors.
    • Supports 100% of OCTARAM protocol standard specification.
    • Supports all the OCTARAM commands as per the specification.
    • Supports device density up to 256MB.
    Block Diagram -- OCTARAM Memory Model
  • ARC EM9D 32-bit DSP Enhanced Processor core based on the ARCv2DSP ISA with CCM and XY Memory
    • Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
    • Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
    • RAM configuration optimized for efficient area and power
    • Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
    Block Diagram -- ARC EM9D 32-bit DSP Enhanced Processor core based on the ARCv2DSP ISA with CCM and XY Memory
  • ARC EM11D Enhanced 32-bit processor core, ARCv2DSP ISA with Cache and XY Memory
    • Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
    • Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
    • RAM configuration optimized for efficient area and power
    • Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
    Block Diagram -- ARC EM11D Enhanced 32-bit processor core, ARCv2DSP ISA with Cache and XY Memory
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