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Compare 62 IP from 23 vendors (1 - 10)
  • ARC EM9D 32-bit DSP Enhanced Processor core based on the ARCv2DSP ISA with CCM and XY Memory
    • Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
    • Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
    • RAM configuration optimized for efficient area and power
    • Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
    Block Diagram -- ARC EM9D 32-bit DSP Enhanced Processor core based on the ARCv2DSP ISA with CCM and XY Memory
  • ARC EM11D Enhanced 32-bit processor core, ARCv2DSP ISA with Cache and XY Memory
    • Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
    • Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
    • RAM configuration optimized for efficient area and power
    • Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
    Block Diagram -- ARC EM11D Enhanced 32-bit processor core, ARCv2DSP ISA with Cache and XY Memory
  • ARC-V RMX-100 ultra-low power 32-bit RISC-V processor for embedded applications
    • 32-bit RISC-V embedded CPU with balanced 3-stage pipeline
    • DSP implementation to extend the RISC-V baseline (RMX-100D)
    • 2 KB to 64 KB instruction L1 cache
    • Up to 2MB instruction and data closely coupled memory (CCM)
  • ARC NPX Neural Processing Unit (NPU) IP supports the latest, most complex neural network models and addresses demands for real-time compute with ultra-low power consumption for AI applications
    • ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.
    • ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.
    • Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.
  • Performance-efficient, ultra-low power, compact ARC SEM security processors help protect against logical, hardware, physical and side-channel attacks
    • ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.
    • ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.
    • Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.
  • RISC-V ARC-V RMX-100 Ultra-low Power 32-bit Processor IP for Embedded Applications
    • RISC, and RISC + DSP 32-bit processors for ultra-low power embedded apps
    • Based on the RISC-V ISA, leveraging standard 32-bit protocols (and extensions)
  • LPDDR5X/5/4X/4 Memory Controller IP
    • Intensive DRAM Utilization
    • Ultra Low Power Consumption
    • Extremely Low Latency
    • Safety & Security
    Block Diagram -- LPDDR5X/5/4X/4 Memory Controller IP
  • High Performance HBM, HBM3 Memory Controller
    • DRAM Supports
    • High Performance
    • Low Power Consumption
    Block Diagram -- High Performance HBM, HBM3 Memory Controller
  • Spin Orbit Torque Magnetic Random-Access Memory
    • With the advent of mobile and handheld electronic devices, the demand for much smaller, faster and ultra-low power systems keeps growing. Yet to meet such needs, the microelectronics industry cannot rely anymore on following Moore’s law like it has for the last decades.
    • Embedded memories, which represent a major part of the circuits silicon area have now become a major contributor to power dissipation in integrated system circuits. To solve these issues, several technologies are intensively investigated to replace existing embedded memories (SRAM and Flash).
    • Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) has been chosen by the industry as the non-volatile memory technology of choice to replace Embedded Flash at advanced technology nodes.
  • Ultra-low power 32-bit processor resistant to physical damage
    • Instruction set: T-Head ISA (32-bit/16-bit variable-length instruction set);
    • Pipeline: 2-stage;
    • General register: 16 32-bit GPRs;
    • Bus interface: Dual bus (instruction bus + data bus);
    Block Diagram -- Ultra-low power 32-bit processor resistant to physical damage
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