cryptography accelerator IP
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APB Post-Quantum Cryptography Accelerator IP Core
- Implements ML-KEM and ML-DSA post-quantum cryptography digital signature standards. The system interface is an microprocessor slave bus (APB, AHB, AXI options are available).
- The design is fully synchronous and requires only minimal CPU intervention due to internal microprogramming sequencer.
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High-Speed Elliptic Curve Cryptography Accelerator for ECDH and ECDSA
- Fully digital design
- Portable to any ASIC or FPGA technology
- Fully standard compliant
- Easy to integrate
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RSA Public Key Cryptography Exponentiation Accelerator
- Low footprint
- High throughput
- 2048-bit length inputs
- Short exponent lengths
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Programmable Root of Trust with Quantum Safe Cryptography acceleration, DPA-resistant & FIA-protected cryptographic accelerators and Caliptra RoTM
- The CryptoManager RT-6xx v3 Root of Trust family from Rambus is the latest generation of fully programmable FIPS 140-3 compliant hardware security cores offering Quantum Safe security by design for data center and other highly secure applications.
- Device and system architects face a growing array of security threats, including the threat of quantum computers. Across applications, one constant is the need for a hardware Root of Trust-based security implementation.
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Programmable Root of Trust with Quantum Safe Cryptography acceleration and DPA-resistant & FIA-protected cryptographic accelerators
- The CryptoManager RT-6xx v3 Root of Trust family from Rambus is the latest generation of fully programmable FIPS 140-3 compliant hardware security cores offering Quantum Safe security by design for data center and other highly secure applications.
- Device and system architects face a growing array of security threats, including the threat of quantum computers. Across applications, one constant is the need for a hardware Root of Trust-based security implementation.
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RSA2-AHB Accelerator Core with AHB Interface
- The core implements the exponentiation operation of the RSA cryptography Q = Pk.
- The operands for the exponentiation: k and P as well as the modulus are programmed into the memory and the calculation is started.
- Once the operation is complete, the result Q can be read through the AHB interface.
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Agile PQC Public Key Accelerator
- Agile IP comprised of HW/FW/SW, adaptable to future standards’ evolution
- Highly configurable IP can be tuned for specific applications with most optimal PPA
- Scalable PQC PKA IP complies with latest NIST PQC algorithms
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Agile Post Quantum Crypto (PQC) Public Key Accelerator - NIST algorithms
- Offloads the computationally intensive parts of public key cryptography
- Support for ARM® AMBA® AHB™/AXI™ and synchronous RAM interfaces
- Integer operations (512-, 768-, 1024-, 1536-, 2048-, 3072-, and 4096-bit)
- ECC-GF(p) operations (160, 192, 224, 256, 384, 512 and 521-bit)
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Agile ECC/RSA Public Key Accelerator with 32-bit ALU
- Offloads the computationally intensive parts of public key cryptography
- Support for ARM® AMBA® AHB™/AXI™ and synchronous RAM interfaces
- Integer operations (512-, 768-, 1024-, 1536-, 2048-, 3072-, and 4096-bit)
- ECC-GF(p) operations (160, 192, 224, 256, 384, 512 and 521-bit)
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Agile ECC/RSA Public Key Accelerator with 128-bit ALU
- Offloads the computationally intensive parts of public key cryptography
- Support for ARM® AMBA® AHB™/AXI™ and synchronous RAM interfaces
- Integer operations (512-, 768-, 1024-, 1536-, 2048-, 3072-, and 4096-bit)
- ECC-GF(p) operations (160, 192, 224, 256, 384, 512 and 521-bit)