Programmable Root of Trust Family With DPA, and FIA and Quantum Safe Cryptography

Overview

The RT-66x Root of Trust IP are fully programmable, FIPS 140-3 compliant (or certified for the RT-660F) hardware security anti-tamper cores offering security by design for data center and other highly-secure applications. The RT-660 protects against a wide range of hardware and software attacks with state-of-the-art anti-tamper security techniques. The RT-660 is a security co-processor, built on a custom-designed 32-bit RISC-V architecture, along with dedicated secure memories.

The RT-660 offers superior anti-tamper attack protection through the implementation of Differential Power Analysis (DPA) countermeasures and state-of-the-art fault injection attack (FIA) protections. The RT-660 implements DPA and FIA protected AES, RSA, and ECC cryptographic accelerator cores. The RT-660 provides hardware implementations of a NIST SP800-90a/b/c compliant TRNG (true random number generator), Public Key Engine (RSA up to 8192 bits and ECC up to 521 bits), AES (all modes), HMAC and SHA-2/-3 crypto accelerators.

The RT-661 adds the OSCCA SM2/3/4 Chinese cryptographic accelerators. The RT-664 takes the robust feature set of the RT-660 and adds a Quantum Safe Engine with FIPS 203 ML-KEM (CRYSTALS-Kyber) and FIPS 204 ML-DSA (CRYSTALS-Dilithium), as well as XMSS and LMS stateful hash acceleration, to safeguard against quantum computer attacks.

The RT-66x IP are the ideal choice for chip and system architects designing FPGA and ASIC solutions for applications requiring the highest level of security.

How the Root of Trust Works

While built upon a RISC-V architecture, the RT-660 RISC-V CPU is a custom implementation designed specifically for security use cases. Rambus employed over 20 years of device security experience to build a security co-processor providing the highest levels of siloed and layered security. The RT-660 is designed for integration into government ASICs and FPGAs, offering secure execution of authenticated user applications, tamper detection and protection, and secure storage and handling of keys and security assets.

The Root of Trust offers a siloed approach to security. While located on the same silicon as the main processor, the secure processing core is physically separated. A layered security approach enforces access to crypto modules, memory ranges, I/O pins, and other resources, and assures critical keys are available through hardware only with no access by software. The Rambus Root of Trust RT-660 supports all commonly deployed host SoC processor architectures, including ARM, RISC-V, x86 and others.

The Rambus Root of Trust supports multi-tenant deployments by offering true multiple root of trust capabilities. Each individual Secure Application can be assigned its own unique keys, meaning permissions and access levels are set completely independent of others. Secure Applications are siloed from each other, ensuring the best approach to security. OEMs can determine access levels and permissions for each and all processes operating within the secure processor.

Dedicated FPGA Configuration

The RT-660 is available in an FPGA configuration for synthesis in programmable logic. This configuration is designed to map optimally (for maximum utilization and frequency) into an FPGA fabric and connect either to on-board or external CPUs. In addition, the RT-660 is expanded with an additional OTP emulation model to overcome the lack of (or limitation of) true nonvolatile one-time programmable memory in certain FPGA families. This module allows storing secure assets in external flash in a secure way.

Secure Applications

Included with the RT-66x Hardware Root of Trust IP are a series of standard secure applications (“containers”) to speed development, including secure boot, identity management, HSM reference, and others. A container development kit (CSDK) is also included to allow the development of custom containers for specific use cases.

Rambus can optionally offer dedicated FIPS 140-3 support packages to its licensees that provide FIPS 140-3 related certification documentation, FIPS test scripts, and dedicated FIPS support.

Deep Anti-Tamper Experience

As the inventor and pioneer of DPA and an acknowledged leader in device security, Rambus is uniquely qualified to provide anti-tamper solutions for the most stringent requirements. Rambus technologies protect more than 9 billion chips per year, and as a US-based, independent company, Rambus has the experience and pedigree to be the solution provider of choice. Rambus has for more than 20 years supplied solutions for government and defense applications, including anti-tamper cores, software libraries, and testing workstations.

Key Features

  • Superior Security
    • Hardware Root of Trust employing a custom 32-bit RISC-V processor
    • Multi-layered security model provides protection of all components in the core
    • NIST CAVP and CMVP compliant for FIPS 140-3 validation
    • FIPS 140-3 CMVP Level 2 certified (RT-660F)
    • State-of-the-art anti tamper techniques
    • DPA-resistant cryptographic accelerators
    • FIA-protected cryptographic accelerators
    • Caliptra* Root of Trust for Measurement with DICE and X.509 support option
    • TRNG and PUF entropy sources
    • Quantum Safe Engine (QSE)
    • Secure lifecycle management
    • Secure provisioning with Rambus CryptoManager Root Server (CMRS)
    • * This is an unofficial implementation of the Caliptra specification. It is not Caliptra certified.
  • Enhanced Flexibility
    • 3rd-party applications run securely within trusted boundary, each with its own assigned security permissions
    • Complete development environment allows OEMs and users to easily develop secure applications (”containers”); standard use case application containers provided
    • Support for secure provisioning of keys and firmware at manufacturing or in the field
    • Support for multiple roots of trust within a single secure core
    • Secure applications can be assigned unique keys, allowing independent permissions and access levels
  • Security Models
    • Hierarchical privilege
    • Secure key management policy
    • Hardware-enforced isolation/access control/protection
    • Error management policy
  • Cryptographic Accelerators
    • RT-660F: NIST CMVP certified. NIST CAVP hardware cryptographic accelerators, including AES (all modes), HMAC, SHA-2/3 (all modes), RSA up to 4096 or 8192 bits, ECC up to 521 bits, and a SP800-90A/B Certified TRNG
    • RT-660: As per RT-660F + LMS and XMSS hash-based signature schemes, SHAKE XOF, NIST CMVP compliant signature schemes, and SHAKE XOF
    • RT-661: As per RT-660 + Chinese Encryption with OSCCA SM2/3/4
    • RT-662 As per RT-660 + IoT Encryption with ChaCha20/Poly1305
    • RT-664: As per RT-660 + Quantum Safe Engine with ML-KEM (CRYSTALS-Kyber) and ML-DSA (CRYSTALS-Dilithium)
  • Security Modules
    • Canary logic for protection against glitching and overclocking
    • Secure key derivation and key transport
    • Life cycle management
    • Secure test and debug
    • Feature management

Benefits

  • Secure co-processor
  • Main processor agnostic
  • Standard secure applications
  • Technology and process node independent

Block Diagram

Programmable Root of Trust Family With DPA, and FIA and Quantum Safe Cryptography Block Diagram

Deliverables

  • Verilog RTL Design database
  • Tools and Scripts for synthesis and simulation
  • Complete verification test bench and comprehensive set of test vectors
  • Complete Documentation Set: Hardware Reference Manual, Integration Guide, HLOS Programmer’s Guide, Developer’s Guide, API Guide
  • Boot loader and firmware, including secure RTOS and security monitor
  • HLOS APIs for accessing capabilities
  • Secure Application SDK with complete development environment, including compiler, assembler, debugger, simulator, reference code, container-authoring software
  • QEMU implementation
  • Implementation of HLOS or ASIC components
  • Sample application demonstrating usage of Secure Application

Technical Specifications

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Semiconductor IP