cryogenic IP

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Cryogenic 12 bit ADC
- Successive Approximation Register (SAR), interleaved 8-fold
- 12 bit default nominal resolution
- 14 bit and 16 bit resolution by in-ADC transparent oversampling, resulting in 12 and 13 ENOB
- 0.7LSB noise, 0.7LSB DNL, 4LSB INL in nominal mode, @RT, BOL
General Purpose I/O

Silvaco develops General Purpose I/O optimized for design flexibility, performance and ESD protection. We also provide specialty I/O, such as high speed LVDS (2Gbs) and SSTL, plus I/O for cryogenic applications.
CryoCMOS IP to Unlock Quantum Computing
- Specially Engineered CryoCMOS IP
- Characterised down to 4°K
- Minimal Power Dissipation
- Reduces Thermal Load
- Standard Cell Library Recharacterisation
- IP Portfolio for Cryo-ASIC’s