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V-by-One IP

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Search (35)
Compare 35 IP from 10 vendors (1 - 10)
  • V-by-One Rx IP, Silicon Proven in SMIC 40LL
    • Wide-range data rate, up to 1Gbps, and the associated clock is DDR clock (1/2 of the data rate, up to 500MHz)
    • 16 channels total 128 bits of parallel data, each channel has a bit width of 8 bits
    • DC coupling mode
    • Multi-channel shared offset
    Block Diagram -- V-by-One Rx IP, Silicon Proven in SMIC 40LL
  • V-by-One Tx IP, Silicon Proven in SMIC 40LL
    • 16 channels total 128 bits of parallel data, each channel has a bit width of 8 bits
    • DC coupling mode
    • Multi-channel shared offset
    • Built-in transmitter terminal impedance, no need for off-chip components
    Block Diagram -- V-by-One Tx IP, Silicon Proven in SMIC 40LL
  • V-by-One 1.4 Receiver
    • Compliant with V-by-One 1.4 specification
    • Support for up to 4 channels, with up to 4 Gbps data rate per channel
    • CDR support to resolve skew problems between clock and data in conventional transfer systems
    • Supports up to 40-bit Deep-Color in RGB/YCbCCr/RGBW/RGB/Y format Digital Video Output with selectable edge clocking
    Block Diagram -- V-by-One 1.4 Receiver
  • V-by-One 1.4 Transmitter
    • Compliant with V-by-One 1.4 specification
    • Support for up to 8 channels, with up to 4 Gbps data rate per channel
    • Supports up to 40-bit Deep-Color in RGB/YCbCCr/RGBW/RGB/Y format Digital Video Output with selectable edge clocking
    • Supports scrambling and 8b/10b encoding
    Block Diagram -- V-by-One 1.4 Transmitter
  • Low Power V-by-One HS SerDes
    • Data rates of <600Mb/s to 4Gb/s
    • Compatible with FibreChannel, JESD 204, V-by-One
    • Separate PLLs for Tx and Rx support a single crystal reference
    Block Diagram -- Low Power V-by-One HS SerDes
  • V-By-One PHY & Controller (Tx+ Rx)
    • Area: 1.224mm2 (1440um x 850um) including IO and ESD
    • Compliant with V-By-One HS 1.4 standard
    • Support 1/2/4/8-lane configuration
    • Support 3/4/5-byte mode
  • V-By-One Receiver_8ch
    • Area: 1.224mm2 (1440um x 850um) including IO and ESD
    • Compliant with V-By-One HS 1.4 standard
    • Support 1/2/4/8-lane configuration
    • Support 3/4/5-byte mode
  • V-by-One Rx IP, Silicon Proven in 40G
    • Wide-range data rate, up to 1Gbps, and the associated clock is DDR clock (1/2 of the data rate, up to 500MHz)
    • 16 channels total 128 bits of parallel data, each channel has a bit width of 8 bits
    • DC coupling mode
    • Multi-channel shared offset
  • V-by-One Tx IP, Silicon Proven in 40G
    • Wide-range data rate, up to 1Gbps, the associated
    • clock is DDR clock (1/2 of the data rate, up to 500MHz)
    • 16 channels total 128 bits of parallel data, each channel has a bit width of 8 bits
    • DC coupling mode
  • V-By-One Transmitter IP
    • Compliant with VByOne specification 1.2/1.3/1.4.
    • Full VBYONE Transmit functionality.
    • Supports 1 to 8 lanes. If needed, we can support custom lane configuration.
    • Supports all byte lengths.
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