IP Catalog > V-by-One

V-by-One IP

Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Search (31)
Compare 31 IP from 10 vendors (1 - 10)
  • VBYONE Verification IP
    • Follows VByOne specification as v1.2/1.3/1.4/1.5
    • Support transmitter and Receiver Mode.
    • Supports upto 32 serial lanes.
    • Supports all byte lengths, color depths, and resolutions.
    Block Diagram -- VBYONE Verification IP
  • VBYONE Synthesizable Transactor
    • Follows VByOne specification as 1.2/1.3/1.4/1.5
    • Support transmitter and Receiver Mode
    • Supports upto 32 serial lanes
    • Supports all byte lengths, color depths, and resolutions
    Block Diagram -- VBYONE Synthesizable Transactor
  • V-By-One Transmitter IIP
    • Compliant with VByOne specification 1.2/1.3/1.4.
    • Full VBYONE Transmit functionality.
    • Supports 1 to 8 lanes. If needed, we can support custom lane configuration.
    • Supports all byte lengths.
    Block Diagram -- V-By-One Transmitter IIP
  • V-By-One Receiver IIP
    • Compliant with VByOne specification 1.2/1.3/1.4.
    • Full VBYONE Receive functionality.
    • Supports 1 to 8 lanes. If needed, we can support custom lane configuration.
    • Supports all byte lengths.
    Block Diagram -- V-By-One Receiver IIP
  • V-By-One PHY & Controller (Tx+ Rx)
    • Area: 1.224mm2 (1440um x 850um) including IO and ESD
    • Compliant with V-By-One HS 1.4 standard
    • Support 1/2/4/8-lane configuration
    • Support 3/4/5-byte mode
  • V-By-One Receiver_8ch
    • Area: 1.224mm2 (1440um x 850um) including IO and ESD
    • Compliant with V-By-One HS 1.4 standard
    • Support 1/2/4/8-lane configuration
    • Support 3/4/5-byte mode
  • V-by-One Rx IP, Silicon Proven in 40G
    • Wide-range data rate, up to 1Gbps, and the associated clock is DDR clock (1/2 of the data rate, up to 500MHz)
    • 16 channels total 128 bits of parallel data, each channel has a bit width of 8 bits
    • DC coupling mode
    • Multi-channel shared offset
  • V-by-One Tx IP, Silicon Proven in 40G
    • Wide-range data rate, up to 1Gbps, the associated
    • clock is DDR clock (1/2 of the data rate, up to 500MHz)
    • 16 channels total 128 bits of parallel data, each channel has a bit width of 8 bits
    • DC coupling mode
  • V-by-One Rx IP, Silicon Proven in SMIC 40LL
    • Wide-range data rate, up to 1Gbps, and the associated clock is DDR clock (1/2 of the data rate, up to 500MHz)
    • 16 channels total 128 bits of parallel data, each channel has a bit width of 8 bits
    • DC coupling mode
    • Multi-channel shared offset
    Block Diagram -- V-by-One Rx IP, Silicon Proven in SMIC 40LL
  • V-by-One Tx IP, Silicon Proven in SMIC 40LL
    • 16 channels total 128 bits of parallel data, each channel has a bit width of 8 bits
    • DC coupling mode
    • Multi-channel shared offset
    • Built-in transmitter terminal impedance, no need for off-chip components
    Block Diagram -- V-by-One Tx IP, Silicon Proven in SMIC 40LL
×
Semiconductor IP