VByOneHS Synthesizable Transactor provides an smart way to verify the VByOneHS component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's VByOneHS Synthesizable Transactor is fully compliant with standard VByOne specification as 1.2/1.3/1.4/1.5 Specification and provides the following features.
VBYONE Synthesizable Transactor
Overview
Key Features
- Follows VByOne specification as 1.2/1.3/1.4/1.5
- Support transmitter and Receiver Mode
- Supports upto 32 serial lanes
- Supports all byte lengths, color depths, and resolutions
- Supports lane skew insertion in transmitter mode
- Supports disparity and invalid code insertion in 8b/10b
- Supports 10 bit, 20 bit, 40 bit parallel interface
- Supports insertion of scrambler errors
- Supports scrambler as in VByOneHS specification
- Support on the fly generation of data
- Supports detection and reporting the following errors
- Invalid control character injection
- Invalid data character injection
- Invalid 10bit code injection
- Sync errors
- Scrambler errors
- Disparity errors
- Alignment errors
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- Synthesiable transactors
- Complete regression suite containing all the VByOneHS testcases
- Examples showing how to connect various components, and usage of Synthesiable VIP
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation also contains User's Guide and Release notes
Benefits
Block Diagram
