TSMC N3 IP
Filter
Compare
178
IP
from
7
vendors
(1
-
10)
-
CAT Trip Sensor, TSMC N3
- Remote thermal sensor
- Central hub
- Small size
-
Thermal Diode with Base Pin, TSMC N3
- Easily integrated
- Sense die temperature using external current source
- Created using standard digital process layers.
- Small size
-
Distributed Thermal Sensor (DTS) Non-Deep NWELL, TSMC N3
- Small remote sensors
- Central hub
- High Accuracy
- High Resolution
-
Distributed Thermal Sensor (DTS) Deep NWELL, TSMC N3
- Small remote sensors
- Central hub
- High Accuracy
- High Resolution
-
In-Chip Monitoring Subsystem for Process, Voltage & Temperature (PVT) Monitoring, TSMC N3
- PVT Subsystem supporting a configurable monitoring fabric
- Measurement of dynamic and static conditions in-chip
- Thermal profiling of silicon devices
- Supply voltage analysis during device ‘mission’ mode
-
Temperature Sensor Non-Deep NWELL, TSMC N3
- Accurately measures Silicon junction temperature
- High Accuracy
- Optional 1 or 2 point calibration (if required)
- Digital interface for simplified chip integration
-
Temperature Sensor Deep NWELL, TSMC N3
- Accurately measures Silicon junction temperature
- High Accuracy
- Optional 1 or 2 point calibration (if required)
- Digital interface for simplified chip integration
-
Voltage Monitor with Digital Output (Multi-domain supply monitoring), TSMC N3
- Accurately measures core supply domain and IO voltages
- Measurement of supply ranges up to 1.5V (with Prescaler)
- Measurement of IR drops between supply pins and critical blocks
- Digital interface for simplified chip integration
-
Process Detector (For DVFS and monitoring process variation), TSMC N3
- Measurement of multiple device types
- Support for custom delay chain structures
- Signature Response on Demand
- Scan-path Inserted
-
MIPI C-PHY v2.0 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (N5, N3)
- Compliant with the latest MIPI C-PHY and D-PHY specifications
- Fully verified IP available in TX, RX, or master and slave configuration, including all analog and digital circuitry
- D-PHY mode includes a clock lane and two or four data lanes, each supporting a maximum of 6.5Gb/s per lane in high- speed modes
- C-PHY mode includes two or three trios, each supporting a maximum of 6.5Gs/s per trio in high-speed modes