In-Chip Monitoring Subsystem for Process, Voltage & Temperature (PVT) Monitoring, TSMC N3

Overview

A full suite of embedded monitoring IP managed by a PVT controller with standard interfaces, creates a complete subsystem dedicated to maximizing performance, optimizing power, reliability and enabling highly accurate in-chip analytics. This In-Chip Sensing and PVT Monitoring IP is available as part of the Synopsys DesignWare® Foundation IP portfolio. It also forms the foundation of the new Synopsys Silicon Lifecycle Management (SLM) platform. SLM enables new levels of insight for both SoC providers as well as their customers to optimize operational activities at each stage of the device and system lifecycles from design to in-field.

Key Features

PVT Subsystem supporting a configurable monitoring fabric
Measurement of dynamic and static conditions in-chip
Thermal profiling of silicon devices
Supply voltage analysis during device ‘mission’ mode
Supports dynamic optimisation schemes (DVFS/AVS)

Benefits

Provides visibility of on chip PVT conditions in real time
Accurate thermal monitoring and management
Monitor and optimize the power distribution network under real conditions
Process speed assessment & characterisation
Delay loop speed characterisation
Age Monitoring
Enhanced reliability
Accurate monitoring during device and IP characterisation
Easy production test solution
Energy and power (DVFS/AVS) optimisation

Applications

Thermal monitoring and management
Power and energy optimization
Process speed assessment
Enhancing reliability

Deliverables

Datasheets
GDSII
LEF (Abstract) view
Liberty timing files & LVS netlist
Verilog model
RTL & Constraints (PVT-Controller)

Technical Specifications

Foundry, Node

TSMC, N3

Maturity

Available on Request

Availability

Available

TSMC

Pre-Silicon: 3nm

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