Synopsys IP
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Secure Storage Solution for OTP IP
- Advanced Security: Encrypted storage in OTP using dynamic root key from SRAM PUF
- System-Level Security Extension: Add-on allows sharing the SRAM PUF to protect chip-level assets
- Flexible Security Configuration: Secure regions within OTP can be tailored to meet specific needs
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Verification IP for AMBA AXI4-Stream
- Native SystemVerilog/Verilog with UVM
- Runs natively on all major simulators
- Reference Verification Platform
- Built-in verification plan and coverage
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Verification IP for AMBA ATB
- Trace Data Transfer (Valid, ready signaling)
- Narrow Trace Data Transfer (Data Valid Bytes signaling)
- Flow Control (Valid, ready signaling)
- Flush Request Response (Flush Valid, Ready signaling with Data transfer)
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Verification IP for AMBA AXI
- Complete protocol support for AXI5, AXI-J/K, AXI4, AXI4-Lite, AXI3
- Programmable number of Managers, Subordinates, and Port Monitors
- Interconnect model
- System Monitor
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Verification IP for Arm AMBA CHI Protocol
- AMBA 5 CHI-A/B/C/D/E/F/G
- Request node, secondary node agents and monitor
- Complete port-level checks
- Supports all interface types
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Verification IP for AMBA APB
- Native SystemVerilog/Verilog with UVM
- Includes primary, secondary, monitor
- Runs natively on all major simulators
- Built-in UVM sequence library
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Verification IP for AMBA AHB
- Complete protocol support for AHB5, AHB3, AHB2, AHB-Lite, and AHB Multi Layer
- Includes primary, secondary, monitor
- Configurable bus model
- Backdoor access to AHB secondary memory
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Verification IP for Arm AMBA ACE Protocol
- Complete protocol support for AMBA ACE 5, H, J and K, ACE4, ACE-Lite, AXI5, AXI4, AXI4-Lite, and AXI3.
- Configurable interconnect model for AXI5, AXI4, AXI, ACE5, and ACE4
- Backdoor access to ACE primary cache
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VIP for Compute Express Link (CXL)
- Native SystemVerilog/UVM
- Source Code Test Suites Available
- Built-in Protocol Checks
- Complete Subsystem Verification Solution
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HBM4 PHY IP
- Supports JEDEC HBM4 DRAMs
- Supports data rates up to 12 Gbps
- Supports up to 32 independent 64-bit memory channels
- Pseudo-channel operation supported to enable up to 64 32-bit pseudo-channels with 2048-bit PHY