SerDes IP
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100G SerDes PAM4 PHY
- The SERDES PHY IP delivers a high-performance, low-power solution for high-speed interfaces up to 112Gbps.
- It supports diverse applications including AI accelerators, data centers, 5G infrastructure, and automotive SoCs.
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SerDes
- High-speed SerDes with ultra-low-power consumption
- Industry’s fastest die to die communications
- Multiprotocol SerDes: HMC, PCIe, SATA, SAS, and USB and more
- High lane count with multiple data rates supported
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SerDes Hard Macro-IP in GlobalFoundries 22FDX
- Low-power, flexible and robust Serializer-de-serializer IP built upon a proven ring-PLL based architecture,
- Support for multiple protocols, as well as custom-designed SerDes to meet specific needs and wide range data rates
- Programmable (De)Serialization width: 8, 10, 16, 20, 32, 40, 64, or 80 bit
- Easy integration; delivered including all supplies, ESD and RDL for your bump pitch
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1-56Gbps Serdes - 7nm (Multi-reference Clock)
- The innovative architecture utilizing advanced DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior reliability, and extreme CDR robustness over a wide range of PVT.
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1-56Gbps Serdes - 7nm (Ultra Low Latency)
- The innovative architecture utilizing advanced DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior reliability, and extreme CDR robustness over a wide range of PVT.
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1-56Gbps Serdes - 7nm (Area-optimized)
- The innovative architecture utilizing advanced DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior reliability, and extreme CDR robustness over a wide range of PVT.
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1-112Gbps Serdes - 7nm
- The innovative architecture utilizing advanced DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior reliability, and extreme CDR robustness over a wide range of PVT.
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1-56Gbps Serdes - 7nm (PPA-optimized)
- The innovative architecture utilizing advanced DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior reliability, and extreme CDR robustness over a wide range of PVT.
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ESD Solutions for Multi-Gigabit SerDes in TSMC 28nm
- A Wirebond and FlipChip compatible <80fF ESD Solutions for Multi-Gigabit SerDes Applications.
- This silicon-proven TSMC 28nm Digital I/O Library delivers a low-capacitance, high-reliability interface solution optimized for advanced semiconductor applications.
- Featuring low-capacitance LVDS differential pairs (<250fF per pin) at 0.8V, this library ensures superior signal integrity for high-speed applications.
