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Compare 940 IP from 66 vendors (1 - 10)
  • ESD Solutions for Multi-Gigabit SerDes in TSMC 28nm
    • A Wirebond and FlipChip compatible <80fF ESD Solutions for Multi-Gigabit SerDes Applications.
    • This silicon-proven TSMC 28nm Digital I/O Library delivers a low-capacitance, high-reliability interface solution optimized for advanced semiconductor applications.
    • Featuring low-capacitance LVDS differential pairs (<250fF per pin) at 0.8V, this library ensures superior signal integrity for high-speed applications.
    Block Diagram -- ESD Solutions for Multi-Gigabit SerDes in TSMC 28nm
  • Programmable PCIe2/SATA3 SERDES PHY on TSMC CLN28HPC
    • Programmable SERDES analog front end that supports 1 to 6+ Gbps standard serial protocols
    • Compact form factor – 0.116 mm2 active silicon area per lane including ESD
    • Industry leading low power – typically 6.3 mW/Gbps (@6Gbps) including termination
    • Minimal latency – 3 UI between parallel transfer and serial transmission
    Block Diagram -- Programmable PCIe2/SATA3 SERDES PHY on TSMC CLN28HPC
  • Programmable Low Power SERDES Receiver on TSMC CLN65LP
    • Programmable SERDES analog receiver that supports 0.6 to 3.75 Gbps standard serial protocols
    • Compact form factor – 0.1 mm2 active silicon area per lane including ESD
    • Industry leading low power – typically 6.8 mW/Gbps including termination
    • Minimal latency – 4 UI between parallel transfer and serial transmission
  • Programmable Low Power SERDES on TSMC CLN40G
    • Programmable SERDES analog front end that supports 1 to 11+ Gbps standard serial protocols
    • Compact form factor – 0.104 mm2 active silicon area per lane including ESD
    • Industry leading low power – typically 5.8 mW/Gbps including termination
    • Minimal latency – 3 UI between parallel transfer and serial transmission
  • Programmable Low Power SERDES on TSMC CLN28HPL
    • Programmable SERDES analog front end that supports 1 to 6+ Gbps standard serial protocols
    • Compact form factor – 0.095 mm2 active silicon area per lane including ESD
    • Industry leading low power – typically 5.6 mW/Gbps including termination
    • Minimal latency – 3 UI between parallel transfer and serial transmission
  • PCIe Express Gen4 / Ethernet SERDES on TSMC CLN5A
    • Industry leading low power PMA macro – 122.9mW per lane at 16Gbps (7.7mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
    • Support for Ethernet protocols and Automotive Grade 2
    • Compact form factor – 0.34 mm2 active silicon area per lane including ESD
    • Minimal latency – 3 UI between parallel transfer and serial transmission
  • PCI Express Gen5 SERDES PHY on Samsung 8LPP
    • Industry leading low power PMA macro – 224mW per lane at 28Gbps (8.0 mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
    • Compact form factor – 0.38 mm2 active silicon area per lane including ESD
    • Minimal latency – 3 UI between parallel transfer and serial transmission
    • Single-lane macro scalable to unlimited link width – x1, x2, x4, x8, x16, etc.
  • PCI Express Gen4 SERDES PHY on Samsung 7LPP
    • Industry leading low power PMA macro – 132.7mW per lane at 16Gbps (8.4mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
    • Compact form factor – 0.32 mm2 active silicon area per lane including ESD
    • Minimal latency – 3 UI between parallel transfer and serial transmission
    • Single-lane macro scalable to unlimited link width – x1, x2, x4, x8, x16, etc.
  • PCI Express Gen4 / Ethernet SERDES on TSMC CLN5
    • Industry leading low power PMA macro – 122.9mW per lane at 16Gbps (7.7mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
    • Support for Ethernet protocols and Automotive Grade 2
    • Compact form factor – 0.34 mm2 active silicon area per lane including ESD
    • Minimal latency – 3 UI between parallel transfer and serial transmission
  • PCI Express Gen3/Enterprise Class SERDES PHY on Samsung 28LPP
    • Industry leading low power PMA macro – 88mW per lane at 8Gbps (11.0 mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
    • Compact form factor – 0.216 mm2 active silicon area per lane including ESD
    • Enterprise class Long Reach 5-tap DFE supporting beyond standard PCIe Channels
    • Minimal latency – 3 UI between parallel transfer and serial transmission
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