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SerDes IP

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Compare 886 IP from 69 vendors (1 - 10)
  • SerDes Hard Macro-IP in GlobalFoundries 22FDX
    • Low-power, flexible and robust Serializer-de-serializer IP built upon a proven ring-PLL based architecture,
    • Support for multiple protocols, as well as custom-designed SerDes to meet specific needs and wide range data rates
    • Programmable (De)Serialization width: 8, 10, 16, 20, 32, 40, 64, or 80 bit
    • Easy integration; delivered including all supplies, ESD and RDL for your bump pitch 
  • Block Diagram -- 16Gbps SerDes IP on TSMC 12nm
  • Extended Long-Reach (XLR) Multi Standard SerDes (MSS) IP
    • The UltraAthenaCORE Extended Long-Reach (XLR) Multi Standard SerDes (MSS) IP is a high-performance, area and latency optimized, DSP-based PHY.
    • It is a highly configurable IP that supports all leading edge NRZ and PAM data center standards from 10 Gbps to 224 Gbps, supporting diverse protocols such as 10/25/50/100/200 Gbps Ethernet and UALink.
  • 1-56Gbps Serdes - 7nm (Multi-reference Clock)
    • The innovative architecture utilizing advanced DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior reliability, and extreme CDR robustness over a wide range of PVT.
  • 1-56Gbps Serdes - 7nm (Ultra Low Latency)
    • The innovative architecture utilizing advanced DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior reliability, and extreme CDR robustness over a wide range of PVT.
  • 1-56Gbps Serdes - 7nm (Area-optimized)
    • The innovative architecture utilizing advanced DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior reliability, and extreme CDR robustness over a wide range of PVT.
  • 1-112Gbps Serdes - 7nm
    • The innovative architecture utilizing advanced DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior reliability, and extreme CDR robustness over a wide range of PVT.
  • 1-56Gbps Serdes - 7nm (PPA-optimized)
    • The innovative architecture utilizing advanced DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior reliability, and extreme CDR robustness over a wide range of PVT.
  • ESD Solutions for Multi-Gigabit SerDes in TSMC 28nm
    • A Wirebond and FlipChip compatible <80fF ESD Solutions for Multi-Gigabit SerDes Applications.
    • This silicon-proven TSMC 28nm Digital I/O Library delivers a low-capacitance, high-reliability interface solution optimized for advanced semiconductor applications.
    • Featuring low-capacitance LVDS differential pairs (<250fF per pin) at 0.8V, this library ensures superior signal integrity for high-speed applications.
    Block Diagram -- ESD Solutions for Multi-Gigabit SerDes in TSMC 28nm
  • Programmable PCIe2/SATA3 SERDES PHY on TSMC CLN28HPC
    • Programmable SERDES analog front end that supports 1 to 6+ Gbps standard serial protocols
    • Compact form factor – 0.116 mm2 active silicon area per lane including ESD
    • Industry leading low power – typically 6.3 mW/Gbps (@6Gbps) including termination
    • Minimal latency – 3 UI between parallel transfer and serial transmission
    Block Diagram -- Programmable PCIe2/SATA3 SERDES PHY on TSMC CLN28HPC
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Semiconductor IP