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Security Processor IP

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Search (149)
Compare 149 IP from 43 vendors (1 - 10)
  • ARC SEM120D Security Processor with DSP for Low Power Embedded Applications
    • Performance-, power- and area-efficient security processors for embedded applications
    • Secure privilege mode orthogonal to kernel/user mode
    • Enhanced secure MPU with context ID for secure or normal operation
    • Up to 16 configurable protected regions and per region scrambling capability
    Block Diagram -- ARC SEM120D Security Processor with DSP for Low Power Embedded Applications
  • ARC SEM110 Security Processor for Low Power Embedded Applications
    • Performance-, power- and area-efficient security processors for embedded applications
    • Secure privilege mode orthogonal to kernel/user mode
    • Enhanced secure MPU with context ID for secure or normal operation
    • Up to 16 configurable protected regions and per region scrambling capability
    Block Diagram -- ARC SEM110 Security Processor for Low Power Embedded Applications
  • ARC SEM130FS Safety and Security Processor
    • ASIL D compliant dual-core, lockstep safety processor supports ISO 26262 automotive safety standards and provides advanced security to protect against evolving threats
    • Secure privilege mode orthogonal to kernel/user mode
    • Integrated self-checking safety monitor capable of time diversity
    • Uniform instruction timing and timing/ power randomization for side channel resistance
    Block Diagram -- ARC SEM130FS Safety and Security Processor
  • IEEE 802.1ae (MACsec) 100G Security Processor with Avalon-ST Interface
    • Small size combined with high performance
    • Self-contained
    • Very low latency
  • IEEE 802.1ae (MACsec) Security Processor
    • Small size combined with high performance:
    • Self-contained, uses two external memories for key storage and statistic counters
    • Very low latency
    • Back-to-back packet processing
    Block Diagram -- IEEE 802.1ae (MACsec) Security Processor
  • IPsec Security Processor
    • Support for IPv4 and IPv6 packets
    • Support for the IPsec ESP and AH protocols:
    • Support for IPsec ESP encryption algorithms per RFC 4835:
    • Support for IPsec ESP (and AH for –AH option) authentication algorithms per RFC 4835:
  • Compact Processor for Security
    • Secure MPU against memory tampering
    • Shields against side-channel attack
    • Secure debug for multi-party software development
    • Flexible configurations and run-time control
    Block Diagram -- Compact Processor for Security
  • Performance-efficient, ultra-low power, compact ARC SEM security processors help protect against logical, hardware, physical and side-channel attacks
    • ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.
    • ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.
    • Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.
  • Neuromorphic Processor IP (Second Generation)
    • Supports 8-, 4-, and 1-bit weights and activations
    • Programmable Activation Functions
    • Skip Connections
    • Support for Spatio-Temporal and Temporal Event-Based Neural Network
    Block Diagram -- Neuromorphic Processor IP (Second Generation)
  • Configurable RISC-V processor IP core
    • The NOEL3 is a configurable RISC-V processor IP core, described in VHDL.
    • The architecture is designed to utilize a small area footprint and to maintain execution predictability.
    Block Diagram -- Configurable RISC-V processor IP core
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