Samsung IP
Filter
Compare
215
IP
from 29 vendors
(1
-
10)
-
USB3.0 PHY on GF22FDX and Samsung 28nm FDSOI
- The USB3.0 PHY IP is designed according to the USB 3.0, USB2.0 Specification.
- It supports the USB3.0 5Gbps Super-Speed mode and backward compatibles with the USB2.0 480Mbps High-Speed, 12Mbps Full-Speed, and 1.5Mbps Low-Speed modes
- The USB 3.0 PHY interface complies with PHY Interface for PCI Express and USB3.0 Architectures specification (PIPE 3.0) and the USB2.0 PHY interface complies with the UTMI v1.05 specification.
-
HSSTP TX PHY 5nm Samsung Foundry
- Samsung Foundry 5nm (SF5A) CMOS device technology
- 1.8V±5%, 0.75V±5% power supply
- Fully supports ARM HSSTP v6.0
- Supports 1.5/3/6Gbps data rates
-
PHY for PCIe 6.0 and CXL for Samsung SF5A
- DSP-based Long Reach (LR) equalization and clock data recovery (CDR) provide superior performance and reliability
- Low active and standby power consumption, supports L1 sub-states standby power management
- Extensive set of isolation, test modes, and loopbacks including APB and JTAG
- Supports lane aggregation and bifurcation
-
HBM2 PHY for Samsung
- Lowest latency for data-intensive applications
- Advanced clocking architecture minimizes clock jitter
- Highest data rates with high-resolution delay adjust
- Designed for optimized interposer routing
-
16b 80Msps DAC with 10KHz BW in samsung 8nm
- Technology: Samsung 8nm LPP process
- Metal Scheme:11M_3Mx_6Dx_1Gx_1Iz_LB
- Programmable Gain
- Programmable Offset
-
12b, 2Gsps, Self-Calibrating Current Steering IQDAC in samsung 8nm for 5G & WIFI6
- Technology: Samsung 8nm LPP process
- Metal Scheme: 11M_3Mx_6Dx_1Gx_1Iz_LB
- 12b Resolution, Fs = 2Gsps
- Programmable 20mA Differential Current source
-
Dual channel 12-bit, 2GS/s ADC for 5G & WIFI6 in Samsung 8nm
- Technology: Samsung 8nm LPP process
- Metal Scheme:11M_3Mx_6Dx_1Gx_1Iz_LB
- Dual channel 12-bit, 2GS/s Analog-to-Digital Converter
-
12-bit, 6MS/s ADC for Microcontroller Business in Samsung LFR6LP
- Process Node: Samsung LFR6LP
- 12-bit SAR ADC @ 6MS/s conversion range.
- The ADC power scales linearly with clock speed. (DC to 6Msps)
- Single-ended/ Differential input modes
-
USB 2.0 PHY for Samsung
- Compliant with USB 2.0 specification and backwards compatible to USB 1.1 specifications
- Supports host, peripherals, and OTG applications
- Supports Battery Charging Specification v1.2
- Supports link power management (LPM)
-
1.8V/3.3V Switchable GPIO With 5V I2C Open - Drain & Analog Cells in Samsung 11nm LPP
- Multi-voltage 1.8V / 3.3V switchable operation
- 4 selectable drive strengths (25-235 MHz @ 1.8V, 10pF
- Full-speed output enable
