Sram IP

The AHB SRAM Controller provides a standard AHB interface to translate AHB bus reads and writes into reads and writes with the signaling and timing of a standard 32-bit synchronous SRAM.
The AHB SRAM Controller provides zero-wait-state AHB access to the synchronous SRAM in all cases except for the following back-toback events: an AHB write directly followed by an AHB read.

SureCore has exploited its low power design capability to create a new range of ultra-low voltage, SRAM solutions, called PowerMiser^™ Plus.
Based on the market-leading, low dynamic power PowerMiser architecture, this dual rail product family can interface down to 0.45V, enabling customers to create innovative, low power products.

Ultra low power data retention. Memory instances generated by the Bulk 40 ULPgo into a deep sleep mode that retains data at minimal power consumption.

Ultra low power data retention. Memory instances generated by the Bulk 22ULL go into a deep sleep mode that retains data at minimal power consumption.
Self biasing. The SP SRAM 22ULL internal self-biasing capabilities provide ease of IP integration.
High yield. To ensure high manufacturing yield, bulk 22ULL uses low leakage 6T (0.110µ2) bit cells and is consistent with Design for Manufacturing (DFM) guidelines for the Bulk 22ULL process.
High usability. All signal and power pins are available on metal 4 while maintaining routing porosity in metal 4. Power pins can optionally be made available on metal 5 to simplify the power connections at the chip level.

SRAM IP