IP Catalog > SRAM

SRAM IP

Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Search (783)
Compare 783 IP from 82 vendors (1 - 10)
  • QDR II SRAM Controller Intel® FPGA IP Function
    • The QDR II SRAM Controller Intel FPGA IP provides an easy-to-use interface to QDR II SRAM and QDR II+ SRAM modules
    • The QDR II SRAM controller ensures that the placement and timing are in line with QDR II specifications
    • The QDR II SRAM controller’s local interface is compatible with the Intel FPGA Avalon® Memory-Mapped interface, for easy integration into Intel Qsys IP.
  • QDR II SRAM Controller Intel® FPGA IP
    • The QDR II SRAM Controller Intel® FPGA IP function provides an easy-to-use interface to QDR II SRAM modules
    • The QDR II SRAM Controller ensures that the placement and timing are in line with QDRII specifications.
  • AHB SRAM Controller
    • The AHB SRAM Controller provides a standard AHB interface to translate AHB bus reads and writes into reads and writes with the signaling and timing of a standard 32-bit synchronous SRAM.
    • The AHB SRAM Controller provides zero-wait-state AHB access to the synchronous SRAM in all cases except for the following back-toback events: an AHB write directly followed by an AHB read.
    Block Diagram -- AHB SRAM Controller
  • Block Diagram -- AXI 5-Master Component Low-Latency SRAM Controller
  • Ultra-low voltage, SRAM
    • SureCore has exploited its low power design capability to create a new range of ultra-low voltage, SRAM solutions, called PowerMiser™ Plus. 
    • Based on the market-leading, low dynamic power PowerMiser architecture, this dual rail product family can interface down to 0.45V, enabling customers to create innovative, low power products.
  • SRAM Memory Model
    • Supports SRAM memory devices from all leading vendors.
    • Supports 100% of SRAM protocol standard.
    • Supports all the SRAM commands as per the specs.
    • Supports Automated power down when deselected.
    Block Diagram -- SRAM Memory Model
  • Bulk 40ULP Single Port SRAM with low power retention mode, high speed pins on 1 side
    • Ultra low power data retention. Memory instances generated by the Bulk 40 ULPgo into a deep sleep mode that retains data at minimal power consumption.
  • Single Port SRAM with low power retention mode, high speed pins on 1 side
    • Ultra low power data retention. Memory instances generated by the Bulk 22ULL go into a deep sleep mode that retains data at minimal power consumption.
    • Self biasing. The SP SRAM 22ULL internal self-biasing capabilities provide ease of IP integration.
    • High yield. To ensure high manufacturing yield, bulk 22ULL uses low leakage 6T (0.110µ2) bit cells and is consistent with Design for Manufacturing (DFM) guidelines for the Bulk 22ULL process.
    • High usability. All signal and power pins are available on metal 4 while maintaining routing porosity in metal 4. Power pins can optionally be made available on metal 5 to simplify the power connections at the chip level.
×
Semiconductor IP