SDIO Controller IP

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Compare 41 IP from 12 vendors (1 - 10)
  • SDIO Host Controller IIP
    • Compliant with SD Host Controller Specification version 4.0
    • Compliant with Part E1 SDIO specification 4.10
    • Supports SDMA, ADMA2 and ADMA3 modes
    • Supports 1-bit, 4-bit bus mode and SPI Bus mode
    Block Diagram -- SDIO Host Controller IIP
  • SDIO Device Controller IIP
    • Compliant with Part 1 Physical Layer Specification Version 3.01 and earlier versions
    • Compliant with Part E1 SD Specification version 3.00 and earlier versions
    • Supports all commands/response types
    • Supports 1-bit, 4-bit ,8 bit SD bus mode and SPI Bus mode
    Block Diagram -- SDIO Device Controller IIP
  • SDIO Slave Controller
    • Compliant with SD Physical Specification Version 2.00 and SDIO Specification Version 2.00.
    • Supports SPI, 1-bit and 4bit SD modes.
    • Supports SDIO Interrupt feature.
    • Supports all mandatory SDIO Commands/Response types
    Block Diagram -- SDIO Slave Controller
  • SDIO to UART Controller
    • Compliant with SD Physical Specification Version 2.00 and SDIO Specification Version 2.00.
    • Supports SPI, 1-bit and 4bit SD modes.
    • Supports SDIO Interrupt feature
    • Supports all mandatory SDIO Commands/Response types
    Block Diagram -- SDIO to UART Controller
  • SD / SDIO / MMC Host Controller
    • Compliant with SD Host Controller Standard Specification Version 2.0
    • Compliant with SD Physical Layer Specification Version 2.0
    • Compliant with SDIO Specification 2.0
    • Compliant with eMMC Specification Version 4.41
    Block Diagram -- SD / SDIO / MMC Host Controller
  • SD 4.1 / SDIO 4.1 / eMMC 4.51 Host Controller IP
    • The SD 4.1/SDIO 4.1 IP from Arasan Chip Systems is a highly integrated host controller IP solution that supports three key memory card I/O technologies.
    • SD 4.1 Host Controller IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds.
    Block Diagram -- SD 4.1 / SDIO 4.1 / eMMC 4.51 Host Controller IP
  • SD 3.0 / SDIO 3.0 / eMMC 5.1 Host Controller IP
    • The SD 3.0 / eMMC 5.1 Host IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds.
    • The IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead.
    Block Diagram -- SD 3.0 / SDIO 3.0 / eMMC 5.1 Host Controller IP
  • SD Card / SDIO Card Combo Device IP
    • SD / SDIO Card Combo Device IP core is SD memory controller and a SDIO controller with an AHB interface.
    • Combining with the optional NAND Flash Controller IP, the SD/SDIO Combo Device IP provides an integrated SD memory Card solution for designs that utilize NAND flash memory.
    Block Diagram -- SD Card / SDIO Card Combo Device IP
  • SDIO Card Device IP
    • The SDIO Card Device IP core is used to implement SDIO cards that are connected to a Host processor over a standard SD bus. The flexible architecture of the SDIO Device IP core is targeted to develop a range of portable, low-power cards such as the WiFi (802.11), GPS, WiMAX, UWB, LTE.
    • The SDIO Card Device IP core is fully compliant with the SD Specification Part E1 SDIO 3.0. It supports SPI, SD1, and SD4 bit transfer modes, and multiple functions per card. High-speed and full-speed SD data transfers are also supported.
    Block Diagram -- SDIO Card Device IP
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Semiconductor IP