SDIO Device Controller IIP

Overview

SDIO DEVICE interface provides full support for the SDIO DEVICE synchronous serial interface, compatible with SD specification part E1 SDIO 3.00 and Part 1 Physical Layer Specification Version 3.01. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. SDIO DEVICE IIP is proven in FPGA environment. The host interface of the SDIO can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

SDIO Device Controller IIP is supported natively in Verilog and VHDL

Key Features

Compliant with Part 1 Physical Layer Specification Version 3.01 and earlier versions
Compliant with Part E1 SD Specification version 3.00 and earlier versions
Supports all commands/response types
Supports 1-bit, 4-bit ,8 bit SD bus mode and SPI Bus mode
Supports CRC7 checking/generation for command/response
Supports CRC16 checking/generation for data transfer
Supports default and high speed modes
Supports SDR12, SDR25 ,DDR50, SDR 50 and SDR104 modes
Supports single byte, single block and multiple block transfer operations
Supports read-write and read-only cards
Supports different memory capacities given below,

Standard Capacity SD Memory Card (SDSC) : Up to 2 GB
High Capacity SD Memory Card (SDHC) : More than 2GB and up to 32GB
Extended Capacity SD Memory Card (SDXC) : More than 32GB and up to and including 2TB

Supports switch function command
Supports block count setting(CMD23) command
Supports direct commands during data transfer
Supports multiple IO functions and one memory
Supports Asynchronous Interrupt to Host Controller
Supports Suspend and Resume operation
Supports Read Wait control operation
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
Simple interface allows easy connection to microprocessor/microcontroller devices

Benefits

Single site license option is provided to companies designing in a single site.
Multi sites license option is provided to companies designing in multiple sites.
Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

Block Diagram

Deliverables

The SDIO DEVICE Controller is available in Source and netlist products.
The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
Easy to use Verilog Test Environment with Verilog Testcases
Lint, CDC, Synthesis, Simulation Scripts with waiver files
IP-XACT RDL generated address map
Firmware code and Linux driver package
Documentation contains User's Guide and Release notes.

Technical Specifications

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