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PPU IP

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Compare 4 IP from 2 vendors (1 - 4)
  • Parallel Processing Unit
    • The Parallel Processing Unit (PPU) is an IP block that integrates tightly with the CPU on the same silicon.
    • It is designed to be highly configurable to specific meet requirements of numerous use cases. 
    Block Diagram -- Parallel Processing Unit
  • NPU IP for Data Center and Automotive
    • 128-bit vector processing unit (shader + ext)
    • OpenCL 1.2 shader instruction set
    • Enhanced vision instruction set (EVIS)
    • INT 8/16/32b, Float 16/32b in PPU
    • Convolution layers
    Block Diagram -- NPU IP for Data Center and Automotive
  • NPU IP for AI Vision and AI Voice
    • 128-bit vector processing unit (shader + ext)
    • OpenCL 3.0 shader instruction set
    • Enhanced vision instruction set (EVIS)
    • INT 8/16/32b, Float 16/32b
    Block Diagram -- NPU IP for AI Vision and AI Voice
  • NPU IP for Wearable and IoT Market
    • ML inference engine for deeply embedded system
      NN Engine
      Supports popular ML frameworks
      Support wide range of NN algorithms and flexible in layer ordering
    Block Diagram -- NPU IP for Wearable and IoT Market
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