Phy IP

Complies with USB specifications, rev. 2.0 and 1.1
Complies with UTMI+ specification, level 3, rev. 1.0
Supports 480Mb/s (HS), 12Mb/s (FS) and 1.5MB/s (LS) serial data transmission rates
Supports 8-bit unidirectional Parallel Interface Engine (PIE) bus for HS, FS and LS modes, and Serial Interface Engine (SIE) for FS and LS modes

The UHS-II PHY IP is a comprehensive, silicon-proven configurable core that has been ported to multiple process nodes and leading foundries.
It uses sub-LVDS signaling consisting of one pair each for transmit, receive, and an additional reference clock. This low-pin interface has reduced power consumption and low EMI.
To further reduce power, the reference clock operates at 1/15 or 1/30 of the data transfer speed.

The ONFI 5.0 PHY IP is designed to connect seamlessly with their ONFI 5.0 Host Controller IP.
The ONFI 5.0 PHY has complete SDR, NV-DDR, NV-DDR2, NV-DDR3 and NV-LPDDR4 TX/RX functionality and supports all the speeds defined in the ONFI specification while remaining backwards compatible with the prior versions of the ONFI specifications.

The NAND Flash Controller IP Core is a full-featured, easy to use, synthesizable core, easily integrated into any SoC or FPGA development.
Designed to support SLC, MLC and TLC flash memories, it is flexible in use and easy in implementation. The controller works with any suitable NAND Flash memory device up to 1024Gb from leading memory providers – Micron, Samsung, Toshiba and Hynix.

Compliant to ONFI revision 3.2 standard
Silicon proven PLL to support all frequencies from 10MHz to 266MHz, and DLL to improve data sampling accuracy dynamically
Include ONFI 3.2 I/O pads compatible to 1.8v NV-DDR2 533 MT/s and 3v NV-DDR 200 MT/s
Supports NV-DDR2 mode of operation supporting up to 266MHz

The I3C bus is used for various sensors in the mobile/automotive system where the Host transfers data and control between itself and various sensor devices.
The I3C interface is intended to improve upon the features of the I2C interface, preserving backward compatibility.

The eMMC5.1 PHY is a fully compliant PHY layer for JEDEC eMMC5.1 and eMMC5.1 JESD84-B50 specification. It is backward compatible with eMMC4.51 and earlier versions of the specifications.
This allows the designers of the SoC to easily support the eMMC interface and optimize the performance and power while maintaining interoperability with eMMC 5.0 and eMMC 5.1 devices.

The xSPI PHY is designed to work with both the xSPI/PSRAM and the xSPI master host controller IPs. When coupled with the ACS xSPI PHY, the combined IPs are able to interact with SPI, Dual SPI, Quad SPI, Octal SPI, and xSPI devices at the full 200 MHz data rate.
This includes both HyperRAM and HyperFlash protocols. Both single and dual data rate modes are supported. The xSPI Master controller IP supports flash devices, whereas the xSPI/PSRAM controller has been designed to support SRAM types of devices using the same interface.