PCIe 3.0 IP
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137
IP
from 20 vendors
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10)
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PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 22ULP
- Compliant with PCIe 3.0 Base Specification
- Compliant with PIPE 4.3
- Supported data transfer rate: 2.5 GT/s, 5.0 GT/s and 8.0 GT/s
- Supported physical lane width: x4
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PCIe 3.0 Serdes PHY IP, Silicon Proven in SMIC 40LP
- Compliant with PCIe 3.0 Base Specification
- Compliant with PIPE 4.3
- Supported data transfer rate: 2.5 GT/s, 5.0 GT/s and 8.0 GT/s
- Supported physical lane width: x4
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PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
- Compliant with PCIe 3.0 Base Specification
- Compliant with PIPE 4.3
- Supported data transfer rate: 2.5 GT/s, 5.0 GT/s and 8.0 GT/s
- Supported physical lane width: x4
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PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- Compliant with PCIe 3.0 Base Specification
- Compliant with PIPE 4.3
- Supported data transfer rate: 2.5 GT/s, 5.0 GT/s and 8.0 GT/s
- Supported physical lane width: x4
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PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 7nm
- Compliant with PCIe 3.0 Base Specification
- Compliant with PIPE 4.3
- Supported data transfer rate: 2.5 GT/s, 5.0 GT/s and 8.0 GT/s
- Supported physical lane width: x4
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PCIe 3.0 Serdes PHY IP, Silicon Proven in GF 22FDX
- Silicon Proven in GF 22GDX with 0.8V and 1.8V power supply.
- Compatible with PCIe base Specification
- Support 32-bit/16-bit parallel interface
- Support for PCIe3(8.0Gbps)
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USB 3.0/ PCIe 2.0 Combo PHY IP, Silicon Proven in TSMC 28HPC+
- Standard PHY interface (PIPE) enables multiple IP sources for PCIe/USB3 MAC layer
- Supports 2.5GT/s and 5.0GT/s serial data transmission rate
- Supports 16-bit or 32-bit parallel interface
- Data and clock recovery from serial stream
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PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 55SP
- Compliant with PCIe 3.0 Base Specification
- Compliant with PIPE 4.3
- Supported data transfer rate: 2.5 GT/s, 5.0 GT/s and 8.0 GT/s
- Supported physical lane width: x4
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PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 40LP
- Compliant with PCIe 3.0 Base Specification
- Compliant with PIPE 4.3
- Supported data transfer rate: 2.5 GT/s, 5.0 GT/s and 8.0 GT/s
- Supported physical lane width: x4
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PCIe 3.0 Serdes PHY IP, Silicon Proven in UMC 28HPC
- Compliant with PCIe 3.0 Base Specification
- Compliant with PIPE 4.3
- Supported data transfer rate: 2.5 GT/s, 5.0 GT/s and 8.0 GT/s
- Supported physical lane width: x4
