PCI Express 6.0 IP
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49
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from 8 vendors
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10)
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IDE Security IP Modules for PCI Express 7.0
- Full support of PCI Express 7.0 (64GT/s) IDE specification
- High-performance AES-GCM based packet encryption, decryption, authentication
- Seamless integration with Synopsys controllers via TLP/FLIT packet-based interface
- FLIT mode support
- Support for PCIe 7.0, 6.0, 5.0, 4.0 and 3.1 data rates
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PCIe 6.0 Retimer Controller with CXL Support
- Designed to the latest PCI Express 6.0 (64 GT/s), and capable of supporting 32.0, 16.0, 8.0, 5.0 and 2.5 GT/s link rates
- Supports x1, x2, x4, x8 and x16 link widths
- CXL aware and supports sync header bypass
- Supports PIPE 5.2/6.1 compatible PHYs
- Optimized data-path for low latency insertion
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PCIe 6.0 (Gen6) Premium Controller with AMBA bridge and LTI & MSI Interfaces
- Supports all required features of the PCI Express 6.2/6.1/6.0.1 (64GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s) and PIPE (32-bit) specifications
- Based on silicon-proven PCIe 6.x controller design
- Allows a full 64GT/s x16 lane bandwidth with up to 1024-bit data path implementations
- Supports advanced RAS data protection features including ECC
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PCIe 6.0 (Gen6) Premium Controller with AMBA bridge
- Supports all required features of the PCI Express 6.2/6.1/6.0.1 (64GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s) and PIPE (32-bit) specifications
- Based on silicon-proven PCIe 6.x controller design
- Allows a full 64GT/s x16 lane bandwidth with up to 1024-bit data path implementations
- Supports advanced RAS data protection features including ECC
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PCIe 6.0 (Gen6) Premium Controller
- Supports all required features of the PCI Express 6.2/6.1/6.0.1 (64GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s) and PIPE (32-bit) specifications
- Based on silicon-proven PCIe 6.x controller design
- Allows a full 64GT/s x16 lane bandwidth with up to 1024-bit data path implementations
- Supports advanced RAS data protection features including ECC
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Adds security Interfaces, features to PCIe 6.0 Premium controllers (Gen6)
- Supports all required features of the PCI Express 6.2/6.1/6.0.1 (64GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s) and PIPE (32-bit) specifications
- Based on silicon-proven PCIe 6.x controller design
- Allows a full 64GT/s x16 lane bandwidth with up to 1024-bit data path implementations
- Supports advanced RAS data protection features including ECC
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PCIe 6.0 Integrity and Data Encryption Security Module
- Compliant with PCI Express IDE specification
- Support for TDISP
- High-performance AES-GCM based packet encryption, decryption, authentication
- Seamless integration with Synopsys controllers via TLP packet-based interface
- FLIT mode support
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PCIe 6.0 / CXL 3.0 PHY & Controller
- Innosilicon’s PCIe 6.0 and CXL 3.0 IP solutions combine high-performance controllers and PHYs, fully compliant with PCIe 6.0, CXL 3.0, and PIPE specifications
- These solutions deliver exceptional performance, low latency, power efficiency, and unparalleled flexibility, making them ideal for enterprise computing, data centers, cloud servers, AI and machine learning, storage expansion, and high-speed interconnect applications
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PHY for PCIe 6.0 and CXL for TSMC 5nm FinFet
- DSP-based Long Reach (LR) equalization and clock data recovery (CDR) provide superior performance and reliability
- Low active and standby power consumption, supports L1 sub-states standby power management
- Extensive set of isolation, test modes, and loopbacks including APB and JTAG
- Supports lane aggregation and bifurcation
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PCIe 6.0 (Gen6) Premium Controller EP/RP/DM/SW 128-1024 bits with AMBA bridge and Advanced HPC Features (Arm CCA)
- Supports all required features of the PCI Express 6.2/6.1/6.0.1 (64GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s) and PIPE (32-bit) specifications
- Based on silicon-proven PCIe 6.x controller design
- Allows a full 64GT/s x16 lane bandwidth with up to 1024-bit data path implementations
- Supports advanced RAS data protection features including ECC
