PCI Express 6.0 IP
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34
IP
from 4 vendors
(1
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10)
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PCIe 6.0 Controller EP/RP/DM/SW with AMBA bridge & HPC features, including Arm Confidential Compute Architecture
- Supports all required features of the PCI Express 6.0, 5.0, 4.0, 3.1, 2.1, and 1.1 specifications
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1 to 64 Gbps PCI-Express (PCIe) 6.0 and CXL 3.0 PHY
- High speed performance
- Low power architecture
- Robust training
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PCIe 7.0 Integrity and Data Encryption (IDE) Security IP Module
- Full support of PCI Express 7.0 (64GT/s) IDE specification
- High-performance AES-GCM based packet encryption, decryption, authentication
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Supports all key features and performance requirements in the CXL 3.0, 2.0, 1.1 and 1.0 specifications
- Supports key required features of the CXL 3.0 specification and full backwards compatibility with CXL 2.0, 1.0 and 1.1
- Supports PCIe 6.0 mode with 64 GT/s and x16 link width
- CXL license includes PCIe 6.0 functionality and fallback mode
- Customers using CXL do not need an additional PCIe 6.0 license
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Configurable controllers for PCIe 6.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications
- Available in all port types including: Endpoint, Embedded Endpoint, Root Complex, Switch Port, Bridge, Dual Mode (Endpoint/Root Complex), and Multi-Port Switch
- Full Transaction Layer, Data Link Layer and Physical Layer
- Supports up to sixteen 64.0, 32.0, 16.0, 8.0, 5.0, 2.5 GT/s lanes
- Available in 32-, 64-, 128-, 256-, 512- or 1024-bit datapath widths for maximum flexibility
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PHY for PCIe 6.0 and CXL for Samsung SF5A
- DSP-based Long Reach (LR) equalization and clock data recovery (CDR) provide superior performance and reliability
- Low active and standby power consumption, supports L1 sub-states standby power management
- Extensive set of isolation, test modes, and loopbacks including APB and JTAG
- Supports lane aggregation and bifurcation
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PHY for PCIe 6.0 and CXL for TSMC 5nm FinFet
- DSP-based Long Reach (LR) equalization and clock data recovery (CDR) provide superior performance and reliability
- Low active and standby power consumption, supports L1 sub-states standby power management
- Extensive set of isolation, test modes, and loopbacks including APB and JTAG
- Supports lane aggregation and bifurcation
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112G PHY G2, TSMC N5 x4, North/South (vertical) poly orientation
- Supports 1.25 to 112 Gbps data-rate
- Supports PCI Express 6.0, 1G to 400G/800G Ethernet, CCIX, CXL, JESD204C, CPRI, SATA, and OIF CEI LR/MR/VSR Electrical Interfaces protocols
- Supports x1 to x16 macro configurations with aggregation and bifurcation
- Spread Spectrum Clock (SSC) support for PCIe
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112G LRM PHY STD, TSMC N4P x4, North/South (vertical) poly orientation
- Supports 1.25 to 112 Gbps data-rate
- Supports PCI Express 6.0, 1G to 400G/800G Ethernet, CCIX, CXL, JESD204C, CPRI, SATA, and OIF CEI LR/MR/VSR Electrical Interfaces protocols
- Supports x1 to x16 macro configurations with aggregation and bifurcation
- Spread Spectrum Clock (SSC) support for PCIe
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112G VSR PHY, TSMC N3P x2, North/South (vertical) poly orientation
- Supports 1.25 to 112 Gbps data-rate
- Supports PCI Express 6.0, 1G to 400G/800G Ethernet, CCIX, CXL, JESD204C, CPRI, SATA, and OIF CEI LR/MR/VSR Electrical Interfaces protocols
- Supports x1 to x16 macro configurations with aggregation and bifurcation
- Spread Spectrum Clock (SSC) support for PCIe
