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Neural Network DSP IP

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Compare 37 IP from 7 vendors (1 - 10)
  • Compact neural network engine offering scalable performance (32, 64, or 128 MACs) at very low energy footprints
    • Best-in-Class Energy
    • Enables Compelling Use Cases and Advanced Concurrency
    • Scalable IP for Various Workloads
    Block Diagram -- Compact neural network engine offering scalable performance (32, 64, or 128 MACs) at very low energy footprints
  • 512-bit Vector DSP IP, Single Core with Functional Safety
    • Integrated hardware safety features with minimal area and power impact for full ASIL compliance (ASIL D systematic, up to ASIL C random)
    • Four-way VLIW architecture combining scalar and vector operations
    • 128-bit, 256-bit and 512-bit vector lengths
    • 8, 16, and 32-bit integer SIMD engines
    Block Diagram -- 512-bit Vector DSP IP, Single Core with Functional Safety
  • 512-bit Vector DSP IP, Quad Core with Functional Safety
    • Integrated hardware safety features with minimal area and power impact for full ASIL compliance (ASIL D systematic, up to ASIL C random)
    • Four-way VLIW architecture combining scalar and vector operations
    • 128-bit, 256-bit and 512-bit vector lengths
    • 8, 16, and 32-bit integer SIMD engines
    Block Diagram -- 512-bit Vector DSP IP, Quad Core with Functional Safety
  • 512-bit Vector DSP IP, Dual Core with Functional Safety
    • Integrated hardware safety features with minimal area and power impact for full ASIL compliance (ASIL D systematic, up to ASIL C random)
    • Four-way VLIW architecture combining scalar and vector operations
    • 128-bit, 256-bit and 512-bit vector lengths
    • 8, 16, and 32-bit integer SIMD engines
    Block Diagram -- 512-bit Vector DSP IP, Dual Core with Functional Safety
  • 512-bit Vector DSP IP, Single Core
    • Four-way VLIW combining scalar and vector operations
    • 128-bit, 256-bit and 512-bit vector word lengths
    • 8, 16, and 32-bit integer SIMD engines
    • IEEE 754-compliant vector floating point unit option offers single-precision or half-precision operations and advanced math functions
    Block Diagram -- 512-bit Vector DSP IP, Single Core
  • 512-bit Vector DSP IP, Quad Core
    • Four-way VLIW combining scalar and vector operations
    • 128-bit, 256-bit and 512-bit vector word lengths
    • 8, 16, and 32-bit integer SIMD engines
    • IEEE 754-compliant vector floating point unit option offers single-precision or half-precision operations and advanced math functions
    Block Diagram -- 512-bit Vector DSP IP, Quad Core
  • 512-bit Vector DSP IP, Dual Core
    • Four-way VLIW combining scalar and vector operations
    • 128-bit, 256-bit and 512-bit vector word lengths
    • 8, 16, and 32-bit integer SIMD engines
    • IEEE 754-compliant vector floating point unit option offers single-precision or half-precision operations and advanced math functions
    Block Diagram -- 512-bit Vector DSP IP, Dual Core
  • 256-bit Vector DSP IP, Single Core with Functional Safety
    • Integrated hardware safety features with minimal area and power impact for full ASIL compliance (ASIL D systematic, up to ASIL C random)
    • Four-way VLIW architecture combining scalar and vector operations
    • 128-bit, 256-bit and 512-bit vector lengths
    • 8, 16, and 32-bit integer SIMD engines
    Block Diagram -- 256-bit Vector DSP IP, Single Core with Functional Safety
  • 256-bit Vector DSP IP, Single Core
    • Four-way VLIW combining scalar and vector operations
    • 128-bit, 256-bit and 512-bit vector word lengths
    • 8, 16, and 32-bit integer SIMD engines
    • IEEE 754-compliant vector floating point unit option offers single-precision or half-precision operations and advanced math functions
    Block Diagram -- 256-bit Vector DSP IP, Single Core
  • 256-bit Vector DSP IP, Dual Core with Functional Safety
    • Four-way VLIW combining scalar and vector operations
    • 128-bit, 256-bit and 512-bit vector word lengths
    • 8, 16, and 32-bit integer SIMD engines
    • IEEE 754-compliant vector floating point unit option offers single-precision or half-precision operations and advanced math functions
    Block Diagram -- 256-bit Vector DSP IP, Dual Core with Functional Safety
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