Mmc emmc device controller IP

The eMMC 5.1 Device Controller IP is compliant with the latest eMMC specification. The controller provides a bandwidth of up to 3.2 Gb/s (400MB/s) in HS400 DDR mode running with a 200 MHz clock.
A NAND Flash controller can be connected to the eMMC controller. In such an implementation, the controller’s AHB interface provides a channel for data transfers between the eMMC device controller and a NAND flash controller (also available from Arasan).

The SD 3.0 / eMMC 5.1 Host IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds.
The IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead.

The SD 4.1/SDIO 4.0/eMMC 5.0 Host IP from Arasan Chip Systems is a highly integrated host controller IP solution that supports three key memory card I/O technologies:
The SD 4.1 / eMMC 5.1 Host IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds. The IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead. In addition, a host can utilize this IP to boot directly from an attached eMMC memory, thereby simplifying system initialization during power up. The host interface is based on a standard 32-bit AHB bus which is used to transfer data and configure the SD 4.1 / eMMC5.1 Host IP.
eMMC 5.1 is backward compatible to the previous versions.

This is a production-ready software stack for Arasan’s SD 3.0/ SDIO 3.0/ eMMC 4.51 Host Controller IP that is used to connect to SD, SDIO, or eMMC devices.
The SD 3.0/eMMC 4.51 stack can also be used for validating a device during its development and integration life cycles thereby helping designers to reduce the time to market for their product.

SD and MMC memory card interfaces dominate the mobile storage markets such as tablets, smartphones, video camcorders, and many other portable or stationary consumer electronics.
Designed to be cost-effective and Linux based this SD 3.0 / eMMC hardware validation platform (HVP) consists of Arasan’s SD3.0/eMMC 4.51 IP mapped into an FPGA offering full-speed physical connectivity to a complementary SoC host or memory card device.

This is a production-ready stack for Arasan’s eMMC Host Controller IP that is used to connect to SD, SDIO, or eMMC devices.
The SD4/SDIO4/eMMC 4.5.1 Stack can also be used for validating a device during its development and integration life cycles thereby helping designers to reduce the time to market for their product.

Host controller for SD and SDIO 3.0 with options to support eMMC 4.41 interface.
Allows host CPU to access SD and MMC devices.
Simple user interface optimized for on-chip bus connection.
Choices of AHB, AXI, APB, PLB, Wishbone, Avalon, SH4 and generic user interface.

Compatible with eMMC/MMC specification 4.41.
Supports Dual Data Rate (DDR) data transfer.
Enhanced MMC features including Boot, Sleep Mode, Reliable Write, Multiple Partitions and Security.
Supports eMMC and Removable Card with option for SD 3.0 device support.

MMC eMMC Device Controller IP