Mipi csi-2 v2.1 IP

Standards Compliant. CSI-2 v2.1, with 8-bit and 16-bit PPI data width and links with 1, 2, 4, or 8 data lanes
Provides up to 8 Independent Stream Output Interfaces, allowing a highly configurable range of options, including multiple pixel modes, various buffering modes, packed data mode, Data Type selection, and Virtual Channel or Data Type interleaving

Arasan IP Core that functions as a MIPI CSI-2 Transmitter, which typically resides in a mobile platform’s camera module, and communicates over a D-PHY/C-PHY link to a CSI2 Receiver in the applications processor.
The Arasan CSI-2 combo IP is MIPI-compliant and provides a standard, scalable, low-power, high-speed interface that supports a wide range of higher image resolutions.

Arasan Chip Systems is a leading System on Chip (SoC) Intellectual Property (IP) provider of a complete suite of Mobile Industry Processor Interface (MIPI) compliant IP solutions, which consists of IP cores, verification IP, software stacks and drivers, protocol analyzers, hardware platforms(HVP’s) for software development and compliance testing and optional customization services.
The Mobile Connectivity (MIPI) compliant IP cores are interface building blocks that simplify interconnect architectures in mobile platforms. This leads to smaller footprint, greater inter-operability between mobile IP, chips and devices from diverse sources and lower power and Electro Magnetic Interface (EMI).
Arasan IP Core that functions as a MIPI Camera Serial Interface (CSI-2 Combo) Receiver, which interfaces between a peripheral device (Camera module) and a host processor (baseband, application engine). The CSI-2 Combo Receiver IP communicates over a D-PHY (or) C-PHY serial link to image processing block, part of the application engine. The Arasan CSI-2 combo IP is MIPI compliance and provides a standard, scalable, low-power, high-speed interface that supports a wide range of higher image resolutions.

PHY Interfaces
Supports D-PHY v2.5, C-PHY v2.0 and A-PHY v1.0 with both PHY interfaces: Serial (Dpdn/ABC/Uplink/downlink) and Parallel (PPI/APPI)
PPI Data Bus Width
Supports 16- and 32-bit PPI data bus width over C-PHYsm

Compliant with MIPI CSI-2 Specification v1.0, v1.1, v1.3, v2.0,v2.1
Compliant with D - PHY Specification v1.1,v1.2,v2.0,v2.1
Compliant with C - PHY Specification v0.7,v1.2,v2.0
Full MIPI CSI-2 TRANSMITTER functionality where either D - PHY / C - PHY can be used