MIPI C-PHY/D-PHY Combo IP
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MIPI C-PHY/D-PHY combo Rx
- MIPI C-PHY v2.0 up to 6.5 Gbps
- 3 trio configuration
- MIPI D-PHY v2.1 up to 6.5Gbps
- 4D-1C configuration
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MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP 4.5Gsps/4.5Gbps
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.1
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
- Consists of 3 Data lanes in C-PHY mode
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MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP in TSMC 40ULP
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 1 Data lanes in D-PHY mode
- Consists of 1 Data Trio in C-PHY mode
- Supports both low-power mode and high-speed mode with integrated SERDES
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MIPI C-PHY/D-PHY Combo CSI-2 TX (Transmitter) in TSMC 40ULP
- Compatible with both C-PHY v1.2 and D-PHY v2.5 specifications for added flexibility.
- All D-PHY subblocks are reused in C-PHY mode for minimum area overhead.
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MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP 3.5Gsps/2.5Gbps
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.1 & C-PHY v1.2
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
- Consists of 3 Data lanes in C-PHY mode
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MIPI C-PHY/D-PHY Combo CSI-2 TX 4.5Gsps/trio in TSMC 28nm
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
- Consists of 3 Data lanes in C-PHY mode
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MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
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MIPI C-PHY/D-PHY Combo CSI-2 TX 3.5Gsps/trio in TSMC 28nm
- Compatible with both C-PHY v2.0 and D-PHY v2.5 specifications for added flexibility.
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MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP 3.5Gsps/2.5Gbps, 2T/2L
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.1 & C-PHY v1.2
- Consists of 1 Clock lane and 2 Data lanes in D-PHY mode
- Consists of 2 Data lanes in C-PHY mode
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MIPI C-PHY/D-PHY Combo RX IP 4.5Gsps/4.5Gbps in TSMC N7
- Dual mode PHY Supports MIPI Alliance Specification D-PHYv2.5 & C-PHYv2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHYmode
