MIPI IP
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893
IP
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MIPI - Enables high-speed, low-power data transfer for displays and cameras
- MIPI (Mobile Industry Processor Interface) is a high-speed, low-power interface designed for video and imaging applications in mobile and embedded devices. It supports DSI for displays and CSI for cameras, ensuring efficient data transfer and high performance.
- MIPI is widely used across mobile devices, automotive systems, wearables, and more. Its scalability, flexibility, and ability to support high-quality video and imaging make it ideal for various industries, including healthcare, VR/AR, and consumer electronics.
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Mipi Unipro Verification IP
- MIPI UniPro VIP is fully compliant with MIPI UniPro Specification 2.0 and MIPI M-PHY Specification 5.0
- Fully supports Transport Layer, Network Layer, Data Link Layer, PHY Adapter Layer and Device Management Entity
- Supports maximum of four Lanes in each direction
- Supports different HS-GEAR or PWM-GEAR in both directions.
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MIPI M-PHY Verification IP
- Compliant to MIPI M-PHY Version 5.0
- Supports two SUB-LINKs with configurable number of LANEs in each
- Supports high speed and low speed modes for all modules
- Supports HS-BURST with all HS-GEARs, HS-G1 to HS-G3 in HS-MODE
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MIPI DSI v2.2 Verification IP
- Compliant to MIPI DSI Specification version 2.2 and MIPI C-PHY Specification version 2.1 with PPI interface.
- Support all Calibration Format & operations
- C-PHY supports MFAA and SFAA for DSI TX and RX respectively for Data Lane Module in command mode.
- C-PHY supports MFAN and SFAN for DSI TX and RX respectively for data Lane Module in video mode.
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MIPI DSI v1.3.2 Verification IP
- Compliant to MIPI DSI Specification version 1.3.2 and MIPI D-PHY Specification version 1.2 with PPI interface.
- Support all Calibration Formats & operations
- D-PHY supports MFAA and SFAA for DSI TX and RX respectively for Data Lane Module in command mode.
- D-PHY supports MFAN and SFAN for DSI TX and RX respectively for Data Lane Module in video mode.
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MIPI D-PHY Verification IP
- Compliant to MIPI D-PHY Specification Version 3.5 with PPI interface.
- Support HS-IDLE State between two data burst.
- Support for Alternate calibration Sequence & Preamble sequence.
- Supports all possible configuration for Data Lane Module and Clock Lane Module at PHY layer.
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MIPI CSI-2 with C-PHY Verification IP
- Compliant to MIPI CSI-2 Specification Version 4.0.1 along with MIPI C-PHY Specification Version 2.1 with PPI interface
- Supports upto 32 virtual channels with C-PHY
- C-PHY supports MFEN and SFEN for CSI-2 TX and RX respectively for Data Lane greater than 1
- C-PHY supports MFAA and SFAA for CSI-2 TX and RX respectively for Data Lane 1 module
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Simulation VIP for MIPI UniPro
- Serial and RMMI Interfaces
- Supports Serial and RMMI interfaces (downstream)
- CPort Signal Interface
- Supports CPort signal interface (upstream)
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Simulation VIP for MIPI SPMI
- Topology
- Multiple subordinates and multiple mains topology
- Clock
- High Speed and Low Speed device classes
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Simulation VIP for MIPI SoundWire-I3S
- PHYs
- Supports LC PHY and DLV PHY
- Interfaces
- Supports serial interface
