Low-power sram IP

Single port, single voltage rail synchronous SRAM
Hierarchical Bit Line – subdividing the array into columns/ rows, banks and local blocks.
Configurable mux factor sets column length and overall aspect ratio
Bit Line Voltage control eliminates potential low operating voltages issues

Single port, single voltage rail synchronous SRAM
Hierarchical Bit Line – subdividing the array into columns/ rows, banks and local blocks.
Configurable mux factor sets column length and overall aspect ratio
Bit Line Voltage control eliminates potential low operating voltages issues

Single port, single voltage rail synchronous SRAM
Hierarchical Bit Line – subdividing the array into columns/ rows, banks and local blocks.
Configurable mux factor sets column length and overall aspect ratio
Bit Line Voltage control eliminates potential low operating voltages issues

Multi-AHB crossbar switch (AXBS) connects multiple masters with various slave IP blocks
External Bus Interface for glueless connection to external memory devices
10/100 Fast Ethernet Controller (FEC) with direct memory access (DMA)
Queued serial peripheral interface (QSPI)

The ApSRAM controller is a flexible, low-power, and low-latency solution designed for SRAM replacement in high-performance systems.
Scalable from 64Mb to 1Gb, its multi-bank architecture enhances timing throughput, making it ideal for wearables, IoT devices, displays, automotive systems, industrial automation, and consumer electronics.
Optimized for AI/ML, edge computing, and high-performance embedded systems, it supports seamless integration through its configurable AXI interface and adaptability across FPGA, Gate array, and Standard cell technologies.

Low-Power SRAM IP