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LDO regulator IP

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Compare 202 IP from 31 vendors (1 - 10)
  • Low input voltage high performance LDO regulator in TSMC 22ULL
    • LDO-T22-1-1.8-0.6-1.05_TSMC_22_ULL is a Low input voltage, high performance LDO linear regulator in TSMC 22ULL with programmable output voltage to supply core logic domains, SRAM arrays or RF/analog domains.
    • It features normal and low-power (LP) operating modes to adjust the amount of output current depending on the application requirements.
    Block Diagram -- Low input voltage high performance LDO regulator in TSMC 22ULL
  • Low Dropout (LDO) Regulator on TSMC 28nm
    • The ODT-LDO-28HPCT is a low dropout (LDO), linear regulator for integration in a SoC.
    • The LDO uses advanced control techniques to achieve excellent transient response, excellent PSRR performance and low noise.
    • The LDO is stable with an off-chip capacitor of 1uF.
    Block Diagram -- Low Dropout (LDO) Regulator on TSMC 28nm
  • LDO regulator on SMIC 40nm, 0.6~1.1v output
    • The present IP is a low dropout voltage regulator, which can support 10uA current load
    • The input voltage is 2.7-3.6V (typical: 3.3V)
    • Its output voltage range is 0.6-0.8-1.1V
    • The reference voltage and bias current are 0.6-0.8-1.1V and 0.5uA from BGR, respectively.
  • LDO regulator on SMIC 40nm, 2.1v output
    • The present IP is a low dropout voltage regulator, which can support 360uA current load
    • The input voltage is 2.7-3.6V (typical: 3.3V)
    • Its output voltage is 2.1V
    • The reference voltage and bias current are 1.2V and 0.5uA from BGR.
  • LDO regulator on SMIC 40nm, 1.13v output
    • The present IP is a low dropout voltage regulator, which can support 10uA DC current load
    • The input voltage is 2.7-3.6V (typical: 3.3V)
    • Its output voltage range is 0.62V-1.13V-1.75V
    • The reference voltage and bias current are 0.6V and 0.5uA from BGR, respectively.
  • LDO regulator on SMIC 40nm, 1.42v output
    • The present IP is a low dropout voltage regulator, which can support 10uA DC current load
    • The input voltage is 2.7-3.6V (typical: 3.3V)
    • Its output voltage range is 0.9V-1.42 V-2.1V
    • The reference voltage and bias current are 0.6V and 0.5uA from BGR, respectively.
  • LDO regulator on SMIC 40nm, up to 12mA
    • The present IP is a low-dropout (LDO) voltage regulator supporting a 12mA load current with an input voltage range of 2.7V to 3.6V (typical: 3.3V)
    • It features three selectable output voltages: 0.9V, 1.1V, and 1.3V
    • The reference voltage and bias current, derived from an integrated bandgap reference (BGR), are 0.6V and 0.5μA, respectively.
  • Capless LDO regulator on SMIC 65nm
    • The present IP is a low-dropout (LDO) and capacitor-less voltage regulator developed using SMIC's 65nm ETOX Nor Flash process
    • It generates adjustable voltages from 0.5V to 4.0V in 0.1V step with a ripple voltage of less than 80mV.
  • Low Dropout Regulator (LDO)
    • High Efficiency: Operates efficiently even at low voltage differences, reducing power consumption and heat dissipation
    • Fast Transient Response: Quickly responds to changes in load, maintaining a stable output voltage
    • Low Noise: Minimizes output noise, crucial for sensitive analog and RF applications
    • Protection Features: Includes over-current, over-temperature, and short-circuit protection to ensure reliability and safety
  • Capless Analog LDO Regulator
    • Output current range is 0-15mA.
    • Short Circuit Current Limiting and Overtemperature Protection
    • Shutdown current< 312nA .
    • DC load regulation< 0.99%
    Block Diagram -- Capless Analog LDO Regulator
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