Ieee 802.3 ethernet phy IP

FEC Sublayer for 100GBASE-CR4 and 100GBASE-KR4 PHY (clause 91 of the IEEE 802.3bj standard).
100G Ethernet MAC-friendly interface

The 1G/10G Ethernet PHY Intel® FPGA Intellectual Property (IP) core supports functionality of both the standard physical coding sublayer (PCS) and the higher data rate 10G PCS with an appropriate physical medium attachment (PMA)
The Standard PCS implements the 1GbE protocol as defined in Clause 36 of the IEEE 802.3 2005 Standard and also supports auto-negotiation as defined in Clause 37 of the IEEE 802.3 2005 Standard
The 10G PCS implements the 10G Ethernet protocol as defined in the IEEE 802.3 2005 standard.

The Multi-Rate Ethernet PHY FPGA IP core can dynamically support multiple data rates without any design regeneration or device reconfiguration
This IP allows the creation of a 1G to 10G configuration that allows dynamic reconfiguration across all Ethernet rates from 10M, 100M, 1G, 2.5G, 5G, and 10G.

Supports 1.25 to 16 Gbps data rates
Supports PCI Express,IEEE 802.3, SGMII and QSGMII,SATA, CEI-6G and CEI-11G, Serial Rapid IO (SRIO), CPRI, OBSAI, JESD204B
Supports x1 to x16 macro configurations

Supports 1.25 to 16 Gbps data rates
Supports PCI Express,IEEE 802.3, SGMII and QSGMII,SATA, CEI-6G and CEI-11G, Serial Rapid IO (SRIO), CPRI, OBSAI, JESD204B
Supports x1 to x16 macro configurations

Supports 1.25 to 16 Gbps data rates
Supports PCI Express,IEEE 802.3, SGMII and QSGMII,SATA, CEI-6G and CEI-11G, Serial Rapid IO (SRIO), CPRI, OBSAI, JESD204B
Supports x1 to x16 macro configurations

IEEE 802.3 Ethernet PHY IP