GDDR6 on Samsung 14LPP IP
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12
IP
from 5 vendors
(1
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10)
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Simulation VIP for GDDR6
- Speed
- Supports up to 16Gbps with current vendor datasheets
- Device Density
- Supports a wide range of device densities from 8Gb to 32Gb
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GDDR6 Synthesizable Transactor
- Supports 100% of GDDR6 protocol standard JESD250, JESD250A, JESD250B and JESD250C specification with version 3.12
- Supports all the GDDR6 commands as per the specs
- Supports 2 separate independent channels with point-to-point interface for data, address and command
- Supports double data rate (DDR) or quad data rate (QDR) data
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GDDR6 Memory Model
- Supports GDDR6 memory devices from all leading vendors.
- Supports 100% of GDDR6 protocol standard JESD250, JESD250A, JESD250B and JESD250C specification with version 3.12.
- Supports all the GDDR6 commands as per the specs.
- Supports 2 separate independent channels with point-to-point interface for data, address and command.
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GDDR6 Controller IIP
- Supports GDDR6 protocol standard JESD250, JESD250A and JESD250B specification with version 3.11.
- Compliant with DFI-version 4.0 or 5.0 Specification.
- Supports all the GDDR6 commands as per the specs.
- Supports up to 16 AXI ports with data width upto 512 bits.
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GDDR6 Assertion IP
- Specification Compliance
- Compliant to ARM GDDR6 protocol
- Supports GDDR6 memory devices from all leading vendors.
- Supports 100% of GDDR6 protocol standard JESD250, JESD250A, JESD250B and JESD250C specification with version 3.12.
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GDDR6 Verification IP
- Compliant to JEDEC GDDR6 SDRAM Specification version JESD250B.
- Supports connection to any GDDR6 Memory Controller IP communicating with a JESD250B compliant GDDR6 Memory Model.
- Supports configurable SDRAM addressing of different sizes (x8 and x16).
- Available in all memory sizes from 4 Gb to 16 Gb per channel.
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GDDR6 Controller
- In-line SEC/DED ECC
- Supports advanced RAS features including error scrubbing, parity, etc.
- Compatible with GDDR6 devices compliant to JESD250b
- Single and multi-port host options for Arm® AMBA®4, AMBA 3 AXI, and low-latency Denali interfaces
- QoS features allow command prioritization
- Flexible paging policy
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GDDR6 Controller
- Supports up to 24 Gb/s per pin operation
- Can handle two x16 GDDR6 channels with one controller or independently with two controllers
- Supports x8 or x16 clamshell mode
- Queue-based interface optimizes performance and throughput
- Maximizes memory bandwidth and minimizes latency via Look-Ahead command processing
- Automatic retry on transactions where EDC error detected
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LPDDR Controller
- Memory controller interface complies with DFI standard up to 5.0
- Application-optimized configurations for fast time to delivery and lower risk
- Sideband and in-line SEC/DED ECC
- Supports advanced RAS features including error scrubbing, parity, etc.
- Compliant to LPDDR5/4X/4/3 protocol memories
- Priority per command on Arm®AMBA® 4 AXI, AMBA 3 AXI
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LPDDR PHY
- Application-optimized configurations for fast time to delivery and lower risk
- Low-power VDD idle, VDD light sleep, and power-efficient clocking in low-speed modes
- I/O pads with impedance calibration logic and data-retention capability
- Fine-grain custom delay cell for delay tuning
- Internal and external datapath loop-back modes
- RX and TX equalization for heavily loaded systems
- Programmable per-bit (PVT compensated) deskew on read and write datapaths