GDDR6 controller IP
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GDDR6 Controller IIP
- Supports GDDR6 protocol standard JESD250, JESD250A and JESD250B specification with version 3.11.
- Compliant with DFI-version 4.0 or 5.0 Specification.
- Supports all the GDDR6 commands as per the specs.
- Supports up to 16 AXI ports with data width upto 512 bits.
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GDDR6 Controller
- In-line SEC/DED ECC
- Supports advanced RAS features including error scrubbing, parity, etc.
- Compatible with GDDR6 devices compliant to JESD250b
- Single and multi-port host options for Arm® AMBA®4, AMBA 3 AXI, and low-latency Denali interfaces
- QoS features allow command prioritization
- Flexible paging policy
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GDDR6 Controller
- Supports up to 24 Gb/s per pin operation
- Can handle two x16 GDDR6 channels with one controller or independently with two controllers
- Supports x8 or x16 clamshell mode
- Queue-based interface optimizes performance and throughput
- Maximizes memory bandwidth and minimizes latency via Look-Ahead command processing
- Automatic retry on transactions where EDC error detected
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GDDR6 PHY IP on GF 12nm LPP
- The UniIC GDDR6 PHY，subsequently referred to as the UNIIC_GD6PHY, is designed for performance and power efficiency, its target is to deliver industry-leading data rates of up to 12Gbps/13Gbps/14Gbps and is compatible with JEDEC standard JEDEC250 and DFI 3.1
- The UNIIC_GD6PHY is used to transfer the Command/Address and Datas between the memory controller and the GDDR6 DRAM device; _x000D_ The UNIIC_GD6PHY is available in Global Foundries FinFET 12LPP technology
- The UNIIC_GD6PHY is fully documented and comes with a comprehensive set of deliverables for ease of system modeling and integration.
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GDDR6 DFI Synthesizable Transactor
- Compliant with DFI version 4.0 or 5.0 Specifications.
- Supports GDDR6 devices compliant with JEDEC GDDR6 SGRAM Standard JESD250A and JESD250B.
- Supports GDDR6 x16 or x8 clamshell modes.
- Can be configured as a single controller driving two x16 GDDR6 channels simultaneously (x32 total) or two controllers each driving one x16 GDDR6 channel.
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GDDR6 DFI Verification IP
- Compliant with DFI version 4.0 or 5.0 Specifications.
- Supports GDDR6 devices compliant with JEDEC GDDR6 SGRAM Standard JESD250A and JESD250B.
- Supports GDDR6 x16 or x8 clamshell modes.
- Can be configured as a single controller driving two x16 GDDR6 channels simultaneously (x32 total) or two controllers each driving one x16 GDDR6 channel.
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GDDR6 DFI Assertion IP
- Specification Compliance
- Compliant with DFI version 4.0 or 5.0 Specifications.
- Supports GDDR6 devices compliant with JEDEC GDDR6 SGRAM Standard JESD250A and JESD250B.
- Supports GDDR6 x16 or x8 clamshell modes.
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GDDR6 Verification IP
- Compliant to JEDEC GDDR6 SDRAM Specification version JESD250B.
- Supports connection to any GDDR6 Memory Controller IP communicating with a JESD250B compliant GDDR6 Memory Model.
- Supports configurable SDRAM addressing of different sizes (x8 and x16).
- Available in all memory sizes from 4 Gb to 16 Gb per channel.
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LPDDR Controller
- Memory controller interface complies with DFI standard up to 5.0
- Application-optimized configurations for fast time to delivery and lower risk
- Sideband and in-line SEC/DED ECC
- Supports advanced RAS features including error scrubbing, parity, etc.
- Compliant to LPDDR5/4X/4/3 protocol memories
- Priority per command on Arm®AMBA® 4 AXI, AMBA 3 AXI
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GDDR6 PHY
- Single configuration supports one GDDR6 device per channel (coplanar) or two GDDR6 devices per channel (clamshell)
- DFI PHY Independent Mode for initialization and training
- Adaptive and continuous timing recovery
- Internal and external datapath loop-back modes
- Transmit crosstalk cancelation of immediate neighbors
- Per-bit DFE, CTLE, and FFE equalization
